View LE58QL021FJC_7676295.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? document id# 080753 date: may 24, 2006 rev: f version: 1 distribution: public document le58ql02/021/031 quad low voltage subscriber li ne audio-processing circuit ve580 series applications ? codec function on telephone switch line cards features ? low-power, 3.3 v cmos technology with 5-v tolerant digital inputs ? software and coefficient compatible to the le79q02/ 021/031 qslac? device ? performs the functions of four codec/filters ? software programmable: ? slic device input impedance ? transhybrid balance ? transmit and receive gains ? equalization (frequency response) ? digital i/o pins ? programmable debouncing on one input ? time slot assigner ? programmable clock slot and pcm transmit clock edge options ? standard microprocessor interface ? a-law, -law, or linear coding ? single or dual pcm ports available ? up to 128 channels (pclk at 8.192 mhz) per pcm port ? optional supervision on the pcm highway ? 1.536, 1.544, 2.048, 3.07 2, 3.088, 4.096, 6.144, 6.176, or 8.192 mhz master clock derived from mclk or pclk ? built-in test modes with loopback, tone generation, and p access to pcm data ? mixed state (analog and digital) impedance scaling ? performance guaranteed over a 12 db gain range ? real time data register wi th interrupt (open drain or ttl output) ? supports multiplexed slic device outputs ? broadcast state ? 256 khz or 293 khz chopper clock for legerity slic devices with switching regulator ? maximum channel bandwidth for v.90 modems ordering information 1. the green package meets rohs directive 2002/95/ec of the european council to minimize the environmental impact of electrical equipment. 2. for delivery using a tape and reel packing system, add a "t" suffix to the opn (ordering part number) when placing an order. device package (green) 1 packing 2 le58ql02fjc 44-pin plcc tube LE58QL021FJC 44-pin plcc tube le58ql021bvc 44-pin tqfp tray le58ql031djc 32-pin plcc tube related literature ? 080754 le58ql061/063 qlslac? device data sheet ? 080761 qslac? to qlslac? device design conversion guide ? 080758 qslac? to qlslac? guide to new designs description the le58ql02/021/031 quad low voltage subscriber line audio-processing circuit (qlslac?) devices integrate the key functions of analog line cards into high-performance, very- programmable, four-channel codec-filter devices. the qlslac devices are based on the proven design of legerity?s reliable slac? device families. the advanced architecture of the qlslac devices implem ents four independent channels and employs digital filters to allow software control of transmission, thus providing a cost-effective solution for the audio-processing function of programmable line cards. the qlslac devices are software and coefficient compatible to the qslac devices. advanced submicron cmos technology makes the le58ql02/ 021/031 qlslac devices economical, with both the functionality and the low power consumption needed in line card designs to maximize line card density at minimum cost. when used with four legerity slic devices, a qlslac device provides a complete software-configurable solution to the borscht functions. block diagram signal processing channel 1 (ch 1) signal processing channel 2 (ch 2) signal processing channel 3 (ch 3) signal processing channel 4 (ch 4) vin 1 vout 1 vin 2 vout 2 vin 3 vout 3 vin 4 vout 4 analog slic clock & reference circuits slic interface (sli) vref cd1 1 cd2 1 c3 1 c4 1 c5 1 cd1 2 cd2 2 c3 2 c4 2 c5 2 cd1 3 cd2 3 c3 3 c4 3 c5 3 cd1 4 cd2 4 c3 4 c4 4 c5 4 time slot assigner (tsa) dxa dra tsca dxb drb tscb microprocessor interface (mpi) int cs dio dclk rst fs pclk mclk/e1 dual/single pcm highway microprocessor chclk
2 le58ql02/021/031 ve580 series data sheet table of contents applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 block descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 clock and reference circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 microprocessor interface (mpi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 time slot assigner (tsa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 signal processing channels (chx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 slic device interface (sli) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 operating ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 environmental ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 electrical ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 transmission characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 attenuation distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 group delay distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 gain linearity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 total distortion including quantizing distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 discrimination against out-of-band input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 discrimination against 12- and 16-khz metering signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 spurious out-of-band signals at the analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 overload compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 switching characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 operating the qlslac device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 channel enable (ec) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 slic device control and data lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 clock mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 e1 multiplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 debounce filters operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 real-time data register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 active state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 inactive state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 chopper clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 overview of digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 two-wire impedance matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 frequency response correction and equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 transhybrid balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
le58ql02/021/031 ve580 series data sheet 3 gain adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 transmit signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 transmit pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 receive signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 receive pcm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 analog impedance scaling network (aisn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 speech coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 signaling on the pcm highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 robbed-bit signaling compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 default filter coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 command description and formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 command field summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 microprocessor interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 summary of mpi commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 mpi command structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 00h deactivate (standby state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 02h software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 04h hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 06h no operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 0eh activate channel (operational state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 40/41h write/read transmit time slot and pcm highway selection . . . . . . . . . . . . . . . . . . . . . .41 42/43h write/read receive time slot and pcm highway se lection . . . . . . . . . . . . . . . . . . . . . .41 44/45h write/read transmit clock slot, receive clock slot, and transmit clock edge . . . . . . .41 46/47h write/read chip configur ation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4a/4bh write/read channel enable and operating mode re gister . . . . . . . . . . . . . . . . . . . . . . .43 4d/4fh read real-time data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 50/51h write/read aisn and analog gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 52/53h write/read slic device input/outp ut register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 54/55h write/read slic input/output direction, read status bits . . . . . . . . . . . . . . . . . . . . . . . .44 60/61h write/read operating functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 6c/6dh write/read interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 70/71h write/read operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 73h read revision code number (rcn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 80/81h write/read gx filter coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 7 82/83h write/read gr filter coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 7 84/85h write/read z filter coefficients (fir and iir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 86/87h write/read b1 filter coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 88/89h write/read x filter coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 8a/8bh write/read r filter coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 96/97h write/read b2 filter coefficients (iir). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 98/99h write/read fir z filter coefficien ts (fir only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 9a/9bh write/read iir z filter coefficients (iir only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 c8/c9h write/read debounce time register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 cdh read transmit pcm data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 e8/e9h write/read ground key filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4 programmable filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 general description of csd coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 5 user test states and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 a-law and -law companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 controlling the slic device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 calculating coefficients with winslac software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 application circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 line card parts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 physical dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4 le58ql02/021/031 ve580 series data sheet 32-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 44-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 44-pin tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 revision a1 to a2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 revision a2 to b1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 revision b1 to c1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 revision c1 to d1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 revision d1 to e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 revision e1 to f1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 list of figures figure 1. le58ql02jc 44-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2. le58ql021jc 44-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3. le58ql031jc 32-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4. le58ql021vc 44-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 5. transmit path attenuation vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 6. receive path attenuation vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 7. group delay distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 8. a-law gain linearity with tone in put (both paths). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 9. -law gain linearity with tone input (both paths). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 10. total distortion with tone input (both paths). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 11. discrimination against out-of-band signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 12. spurious out-of-band signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 13. analog-to-analog overload compre ssion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 14. input and output waveforms for ac tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 15. microprocessor interface (input mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 16. microprocessor interface (output mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 17. pcm highway timing for xe = 0 (transmit on nega tive pclk edge) . . . . . . . . . . . . . . . . . . .24 figure 18. pcm highway timing for xe = 1 (transmit on positi ve pclk edge) . . . . . . . . . . . . . . . . . . . .25 figure 19. master clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 20. clock mode options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 21. slic device i/o e1 multiplex and real-time data register operation. . . . . . . . . . . . . . . . . . .28 figure 22. e1 multiplex internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 23. mpi real-time data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 24. qlslac device transm ission block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 25. robbed-bit frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 26. le7920 slic/qlslac device applic ation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 list of tables table 1. qlslac device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 2. 0 dbm0 voltage definitions with un ity gain in x, r, gx, gr, ax, and ar . . . . . . . . . . . . . . . . .13 table 3. channel parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 4. channel monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 5. global chip parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 6. global chip status monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 7. a-law: positive input values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 8. -law: positive input values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
le58ql02/021/031 ve580 series data sheet 5 product description the qlslac device performs the codec/filter and two-to-four-wire conversion functions required of the subscriber line interface circuitry in telecommunications equipment . these functions involve converting audio signals into digital pcm samples and converting digital pcm samples back into audio signals. during conversion, digital filters are used to band limit the voice sig nals. all of the digital filtering is performed in digital signal proc essors operating from a master clock, which can be derived eith er from pclk or mclk. four independent channels allow the qlslac device to function as four slac? devices. for programming information, each channel has its own enable bit (ec1, ec2, ec3, and ec4) to allow individual channel programming. if more than one channel enable bit is high or if all channel enable bits are high, a ll channels enabled will receive the programming information writte n; therefore, a broadcast mo de can be implemented by simply enabling all channel s in the device to receive the information. the channel enable bits are contained in the channel enable (ec) register, which is written and read using command 4a/4bh. the broadcast mode is useful in initializi ng qlslac devices in a large system. the user-programmable filters set the receive and transmit gain , perform the transhybrid balanc ing function, permit adjustment of the two-wire termination impedance, and prov ide equalization of the receive and transm it paths. all programmable digital fil ter coefficients can be calculated using the winslac? software. data transmitted or received on the pcm highway can be 8-bit companded code (with an optional 8-bit signaling byte in the transmit direction) or 16-bit linear code . the 8-bit codes appear 1 byte per time slot, while the 16-bit code appears in two consecutive time slots. the compressed pcm codes can be either 8-bit companded a-law or -law. the pcm data is read from and written to the pcm highway in user-programmable time slots at rates of 128 khz to 8.192 mhz. the transmit clock edge and clock slot can be selected for compat ibility with other devices that can be connected to the pcm highway. three configurations of the qlslac device are offer ed with single or dual pcm highways. the le58ql02 and le58ql021 qlslac devices with dual and single pcm highways respectively are available in the 44-pin packages. the le58ql031jc qlslac device is a single pcm highway version in a 32-pin plcc package. block descriptions clock and reference circuits this block generates a master clock and a frame sync signal for t he digital circuits. it also generates an analog reference vol tage for the analog circuits. microprocessor interface (mpi) this block communicates with the external control microprocessor over a serial interf ace. it passes user control information to the other blocks, and it passes status info rmation from the blocks to the user. in ad dition, this block contains the reset circ uitry. time slot assigner (tsa) this block communicates with the pcm highway, where the pcm hi ghway is a time division mutiplexed bus carrying the digitized voice samples. the block implements programmable time slots and clocking arrangements in order to achieve a first layer of switching. internally, this block communicate s with the signal processing channels (chx). signal processing channels (chx) these blocks do the transmission proc essing for the voice ch annels. part of the processing is analog and is inte rfaced to the v in and vout pins. the remainder of the processing is digital and is interfaced to the time slot assigner (tsa) block. slic device interface (sli) this block communicates digitally with the slic device circuits. it sends control bits to the slic devices to control modes and to operate leds and optocouplers. it also accepts supervision in formation from the slic devices and performs some filtering. table 1. qlslac device configurations pcm highway programmable i/o per channel chopper clock package part number dual four i/o yes 44 plcc le58ql02jc single five i/o no 44 plcc/tqfp le58ql021jc (or vc) single two i/o no 32 plcc le58ql031jc
6 le58ql02/021/031 ve580 series data sheet connection diagrams figure 1. le58ql02jc 44-pin plcc cd1 3 cd2 3 c3 3 c4 3 cd1 4 cd2 4 c3 4 c4 4 drb dra vout 1 vin 1 vout 2 vin 2 vcca vref agnd vin 3 vout 3 vin 4 vout 4 cd1 2 cd2 2 c3 2 c4 2 cd1 1 cd2 1 c3 1 c4 1 chclk le58ql02jc 44-pin plcc 6 5 4 3 2 1 44 43 42 41 40 29 30 31 32 33 34 35 36 37 38 39 18 19 20 21 22 23 24 25 26 27 28 17 16 15 14 13 12 11 10 9 8 7 mclk/e1 cs dclk dio tsca rst fs tscb dxa dgnd vccd pclk dxb int
le58ql02/021/031 ve580 series data sheet 7 figure 2. le58ql021jc 44-pin plcc figure 3. le58ql031jc 32-pin plcc cd1 3 cd2 3 c3 3 c4 3 c5 3 cd1 4 cd2 4 c3 4 c4 4 c5 4 dra vout 1 vin 1 vout 2 vin 2 vcca vref agnd vin 3 vout 3 vin 4 vout 4 cd1 2 cd2 2 c3 2 c4 2 c5 2 cd1 1 cd2 1 c3 1 c4 1 le58ql021jc 44-pin plcc 6 5 4 3 2 1 44 43 42 41 40 29 30 31 32 33 34 35 36 37 38 39 18 19 20 21 22 23 24 25 26 27 28 17 16 15 14 13 12 11 10 9 8 7 c5 1 mclk/e1 cs dclk dio rst tsca dxa dgnd vccd pclk fs int cd1 2 cd2 2 cd1 1 cd2 1 mclk/e1 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 cd1 3 cd2 3 cd1 4 cd2 4 dra vin 4 vout 3 vin 3 vref agnd vin 2 vout 2 vin 1 le58ql031jc 32-pin plcc vout 4 vout 1 vcca cs int dxa dgnd vccd fs pclk dclk dio tsca rst
8 le58ql02/021/031 ve580 series data sheet figure 4. le58ql021vc 44-pin plcc le58ql021vc 44-pin tqfp 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 44 43 42 41 40 39 38 37 36 35 34 5 6 7 8 9 10 11 4 3 2 1 dio dclk cs tsca dgnd pclk vccd dxa fs rst int vout 2 vin 1 vout 1 vin 2 vcca vref agnd vin 3 vout 3 vin 4 vout 4 c3 3 cd2 3 cd1 3 c4 3 c5 3 cd1 4 cd2 4 c3 4 c4 4 c5 4 dra c3 2 cd2 2 cd1 2 c4 2 c5 2 cd1 1 cd2 1 c3 1 c4 1 c5 1 mclk/e1
le58ql02/021/031 ve580 series data sheet 9 pin descriptions pin names type description agnd, dgnd power separate analog and digital grounds are provided to allow noise isolation; however, the two grounds are connected inside the part, and the grounds must also be connected together on the circuit board. cd1 1 ?cd1 4 , cd2 1 ?cd2 4 inputs/outputs control and data. cd1 and cd2 are ttl compatible programmable input or output (i/o) ports. they can be used to monitor or control the state of the slic drivce or any other device associated with the subscriber line interface. the direction, input or output, is programmed using mpi command 54/55h. as outputs, cd1 and cd2 can be used to control relays, illuminate leds, or perform any other function requiring a latched ttl compatible signal for control. the output state of cd1 and cd2 is written using mpi command 52h. as inputs, cd1 and cd2 can be processed by the qlslac device (if programmed to do so). cd1 can be debounced before it is made available to t he system. the debounce time is programmable from 0 to 15 ms in 1 ms increments using mpi command c8/c9h. cd2 can be filtered using the up/down counter facility and programming th e sampling interval using mpi command e8/ e9h. additionally, cd1 can be demultiplexed into two separate inputs using the e1 demultiplexing function. the e1 demultiplexing function of the qlslac device was designed to interface directly to legerity slic devices supporting the ground key function. with the proper legerity slic device and the e1 function of the qlslac device enabled, the cd1 bit can be demultiplexed into an off-hook/ring trip si gnal and ground key signal. in the demultiplex mode, the second bit, ground key, takes the place of the cd2 as an input. the demultiplexed bits can be debounced (cd1) or filtered (cd2) as explained previously. a more complete description of cd1, cd2, debouncing, and filtering functions is contained in operating the qlslac device , on page 26 . once the cd1 and cd2 inputs are processed (debounced, filtered and/or demultiplexed) by the qlslac device, the information can be access ed by the system in two ways: 1) on a per channel basis along with c3, c4, and c5 of t he specific channel using mpi command 53h, or 2) by using mpi command 4d/4fh, which obtain the cd1 and cd2 bits from all four channels simultaneously. this feature reduces the proces sor overhead and the time required to retrieve time-critical signals from the line circuits, such as off-hook and ring trip. with this feature, hookswitch status and ring trip information, for example, can be obtained from all four channels of a qlslac device with one read command. c3 1 ?c3 4 , c4 1 ?c4 4, c5 1 ?c5 4 inputs/outputs control. c3, c4, and c5 are ttl-compatible programmable input or output (i/o) ports. they can be used to monitor or control the state of the slic device or any other device associated with subscriber line interface. the directi on, input or output, is programmed using mpi command 54/55h. as outputs, c3, c4, and c5 can be used to control relays, illuminate leds, or perform any other function requiring a latched ttl compatible signal for control. the output state of c3, c4, and c5 is written using mpi command 52h. as inputs, c3, c4, and c5 can be accessed by the system by using mpi command 53h. the le58ql021 qlslac device contains a singl e pcm highway and five programmable i/ os per channel (cd1, cd2, c3, c4, and c5) in a 44-pin plcc or tqfp package. in the le58ql02 qlslac device, the c5 1 , c5 2 , c5 3 , and c5 4 i/os are eliminated, enabling dual pcm highways and a chopper clock output in a 44-pin plcc or tqfp package. in the le58ql031 qlslac device, the c3 1 ?c5 1 , c3 2 ?c5 2 , c3 3 ?c5 3 , and c3 4 ?c5 4 i/os are eliminated, enabling a single pcm highway and two control and data i/os (cd1, cd2) per channel in a 32-pin plcc package. chclk output chopper clock. this output pr ovides a 256 khz or a 292.57 khz, 50% duty cycle, ttl- compatible clock for use by up to four slic devices with built-in switching regulators. the chclk frequency is synchronous to the master clock, but the phase relationship to the master clock is random. the chopper clock is not available in all package types. cs input chip select. the chip select input (active low ) enables the device so that control data can be written to or read from the part. the channels selected for the write or read operation are enabled by writing 1 s to the appropriate bits in the channel enable register of the qlslac device prior to the command. see ec1, ec2, ec3, and ec4 of the command 4a/4bh write/ read channel enable and operating mode register , on page 43 for more information. if chip select is held low for 16 rising edges of dclk, a hardware reset is executed when chip select returns high. dclk input data clock. the data clock input shifts data into and out of the microprocessor interface of the qlslac device. the maximum clock rate is 8.192 mhz. dio input/output data. control data is serially written into and read out of the qlslac device via the dio pin, with the most significant bit first. the data clock determines the data rate. dio is high impedance except when data is being tran smitted from the qlslac device.
10 le58ql02/021/031 ve580 series data sheet dra, drb inputs pcm data receive a/b. the pcm data for channels 1, 2, 3, and 4 is serially received on either the dra or drb port during user-programmed time slots. data is always received with the most significant bit first. for compressed sign als, 1 byte of data for each channel is received every 125 s at the pclk rate. in the linear state, two consecutive bytes of data for each channel are received every 125 s at the pclk rate. drb is not available on all package types. dxa, dxb outputs pcm data transmit. the transmit data from channels 1, 2, 3, and 4 is sent serially out on either the dxa or dxb port or both ports during user-programmed time slots. data is always transmitted with the most significant bit first. the output is available every 125 s and the data is shifted out in 8-bit (16-bit in linear or pc m signaling state) bursts at the pclk rate. dxa and dxb are high impedance between time slots, while the device is in the inactive state with no pcm signaling, or while the cutoff transmit pa th bit (ctp) is on. dxb is not available on all package types. fs input frame sync. the frame sync pulse is an 8 khz si gnal that identifies time slot 0, clock slot 0 of a system?s pcm frame. the qlslac device references individual ti me slots with respect to this input, which must be synchronized to pclk. int output interrupt. int is an active low output signal which is programmable as either ttl compatible or open drain. the int output goes low any time one of the input bits in the real time data register changes state and is not masked. it also goes low any time new transmit data appears if this interrupt is armed. int remains low until the appropriate register is read via the microprocessor interface, or the qlslac dev ice receives either a software or hardware reset. the individual cd xy bits in the real time data register can be masked from causing an interrupt by using mpi command 6c/6dh. the transmit data interrupt must be armed with a bit in the operating conditions register. mclk/e1 input/output master clock (input)/enable cd1 multiplex (o utput). the master clock can be a 1.536 mhz, 1.544 mhz, or 2.048 mhz (times 1, 2, or 4) cloc k for use by the digital signal processor. if the internal clock is derived from the pcm clock input (pclk), this pin can be used as an e1 output to control legerity slic devices having multiplexed hookswitch and ground-key detector outputs. pclk input pcm clock. the pcm clock determines the rate at which pcm data is serially shifted into or out of the pcm ports. pclk is an integer multiple of the frame sync frequency. the maximum clock frequency is 8.192 mhz and the mini mum clock frequency is 128 khz for dual pcm highway versions and 256 khz for single pcm highway versions. the minimum clock rate must be doubled if linear state or pcm signal ing is used. pclk frequencies between 1.03 mhz and 1.53 mhz are not allowed. optionally, the digital signal processor clock can be derived from pclk rather than mclk. rst input reset. a logic low signal at this pin resets t he qlslac device to its default state. the rst pin may be tied to vccd if it is not needed in the system. tsca, tscb outputs time slot control. the time slot control outputs are open drain outputs (requiring pull-up resistors to vccd) and are normally inactive (high impedance). tsca or tscb is active (low) when pcm data is transmitted on the dxa or dxb pin respectively. vcca, vccd power analog and digital power supply inputs. vcca and vccd are provided to allow for noise isolation and proper power supply decoupling te chniques. for best performance, all of the vcc power supply pins should be connected togethe r at the connector of the printed circuit board. vin 1 ?vin 4 inputs analog input. the analog voice band signal is applied to the vin input of the qlslac device. the vin input is biased at vref by a large in ternal resistor. the audio signal is sampled, digitally processed and encoded, and then made available at the ttl-compatible pcm output (dxa or dxb). if the digitizer saturates in the pos itive or negative direction, vin is pulled by a reduced resistance toward agnd or vccd, respectively. vin 1 is the input for channel 1, vin 2 is the input for channel 2, vin 3 is the input for channel 3, and vin 4 is the input for channel 4. vout 1 ? vout 4 outputs analog output. the received digital data at dra or drb is processed and converted to an analog signal at the vout pin. vout 1 is the output from channel 1, vout 2 is the output for channel 2, vout 3 is the output from channel 3, and vout 4 is the output for channel 4. the vout voltages are referenced to vref. vref output analog voltage reference. the vref output is provided in order for an external capacitor to be connected from vref to ground, filtering noise present on the internal voltage reference. vref is buffered before it is used by internal circuitry. the voltage on vref and the output resistance are given in electrical characteristics , on page 12 . the leakage current in the capacitor must be low. pin names type description
le58ql02/021/031 ve580 series data sheet 11 absolute maximum ratings stresses above those listed under "absolute maximum ratings" ma y cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. package assembly the green package devices are assembled with enhanced environm ental compatible lead (pb), halogen, and antimony-free materials. the leads possess a matte-tin plating which is comp atible with conventional board a ssembly processes or newer lead- free board assembly processes. the peak soldering temperature should not exceed 245c during printed circuit board assembly. refer to ipc/jedec j-std-020b table 5-2 for the recommended solder reflow temperature profile. operating ranges legerity guarantees the performance of this device over commercial (0 to 70o c) and industrial (-40 to 85oc) temperature ranges by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to periodic sampling. these characterization and test procedures comply with secti on 4.6.2 of bellcore gr-357-core component reliability assurance requirements for telecommunications equipment. environmental ranges electrical ranges storage temperature ?60 c < t a < +125 c ambient temperature, under bias ?40 c < t a < +85 c ambient relative humidity (non condensing) 5 to 95% v cca with respect to agnd ?0.4 to + 4.0 v v cca with respect to vccd 0.4 v v ccd with respect to dgnd ?0.4 to + 4.0 v v in with respect to agnd ?0.4 v to (v cca + 0.4 v) agnd with respect to dgnd 50 mv digital pins with respect to dgnd ?0.4 to 5.5 v or vccd + 2.37 v, whichever is smaller total combined cd1?c5 current per device: source from vccd 40 ma sink into dgnd 40 ma latch up immunity (any pin) 100 ma total vcc current if rise rate of vcc > 0.4 v/s 0.5 a ambient temperature ?40 c < t a < +85 c ambient relative humidity 15 to 85% analog supply v cca +3.3 v 5% v ccd 50 mv digital supply v ccd +3.3 v 5% dgnd 0 v agnd 10 mv cfil capacitance: vref to agnd 0.1 f 20% digital pins dgnd to +5.25 v
12 le58ql02/021/031 ve580 series data sheet electrical characteristics typical values are for ta = 25o c and nominal supply voltages . minimum and maximum values are over the temperature and supply voltage ranges shown in o perating ranges, except where noted. symbol parameter descriptions min typ max unit note v il digital input low voltage 0.8 v v ih digital input high voltage 2.0 i il digital input leakage current a 0 < v < vccd ?7 +7 otherwise ?120 +180 v hys digital input hysteresis 0.16 0.25 0.34 v v ol digital output low voltage cd1?c5 (i ol = 4 ma) cd1?c5 (i ol = 8 ma) tsca , tscb (i ol =14 ma) other digital outputs (i ol = 2 ma) 0.4 0.8 0.4 0.4 v1 v oh digital output high voltage cd1?c5 (i oh = 4 ma) cd1?c5 (i oh = 8 ma) other digital outputs (i oh = 400 a) v ccd ? 0.4 v v ccd ? 0.8 v 2.4 v1 i ol digital output leakage current (h i z state) 0 < v < vccd ?7 +7 a otherwise ?120 +180 gin input attenuator gain dgin = 0 dgin = 1 0.6438 1 v/v v ir analog input voltage range (relative to vref) ax = 0 db, attenuator on (dgin = 0) ax = 6.02 db, attenuator on (dgin = 0) ax = 0 db, attenuator off (dgin = 1) ax = 6.02 db, attenuator off (dgin = 1) 1.584 0.792 1.02 0.51 vpk v ios offset voltage allowed on vin ?50 50 mv z in analog input impedance to vref, 300 to 3400 hz 600 1400 k ? i ip current into analog input for an input voltage of 3.3 v 50 115 a 2 i in current out of analog input for an input voltage of ?0.3 v 50 130 2 z out vout output impedance 1 10 ? cl out allowable capacitance, v out to agnd 500 pf i out vout output current (f< 3400 hz) ?4 4 mapk 3 v ref vref output open circuit voltage (leakage < 20 na) 1.43 1.5 1.57 v z ref vref output impedance (f < 3400 hz) 70 130 k ? v or vout voltage range(ar = 0 db) (relative to vref)(ar = 6.02 db) 1.02 0.51 vpk v oos vout offset voltage (aisn off) ?40 40 mv 4 v oosa vout offset voltage (aisn on) ?80 80 g aisn aisn gain - expected gain (input = 0 dbm0, 1014 hz) attenuator on (dgin = 0) attenuator off (dgin = 1) ?0.016 ?0.024 0.016 0.024 v/v pd power dissipation all channels active 1 channel active all channels inactive 130 40 13 170 80 18 mw c i digital input capacitance 10 pf c o digital output capacitance 10 psrr power supply rejection ratio (1.02 khz, 100 mv rms , either path, gx = gr = 0 db) 40 db
le58ql02/021/031 ve580 series data sheet 13 notes: 1. the cd1, cd2, c3?c5 outputs are resistive for less than a 0.8 v drop. total current must not exceed absolute maximum ratings. 2. when the digitizer saturates, a resistor of 50 k ? 20 k ? is connected either to agnd or to v cca as appropriate to discharge the coupling capacitor. 3. when the qlslac device is in the inactive state, the analog ou tput will present either a vref dc output level through a 15 k ? resistor (vmode = 0) or a high impedance (vmode = 1). 4. if there is an external dc path from vout to vin with a gain of g dc and the aisn has a gain of h aisn , then the output offset will be multiplied by 1 / [1 ? (h aisn ? g dc )]. 5. power dissipation in the inactive state is measured with al l digital inputs at vih = vccd and vil = dgnd and with no load con nected to vout1, vout2, vout3, or vout4. transmission characteristics when relative levels (dbm0) are used in any of the following tr ansmission specifications, the specification holds for any setti ng of the gx gain from 0 db to 12 db, the gr loss from 0 db to 12 db, and the input attenuator (gin) on or off. notes: 1. see figure 5 and figure 6. 2. 0 dbm0 input signal, 300 hz to 3400 hz; measur ement at any other frequency, 300 hz to 3400 hz. 3. no single frequency component in the range above 3800 hz may exceed a level of ?55 dbm0. 4. the weighted average of the crosstalk is defined by the following equation, where c(f) is the crosstalk in db as a function o f frequency, f n = 3300 hz, f 1 = 300 hz, and the frequency points (f j , j = 2..n) are closely spaced: table 2. 0 dbm0 voltage definitions with un ity gain in x, r, gx, gr, ax, and ar signal at digital interface transmit (dgin = 0) transmit (dgin = 1) receive unit a-law digital mw or equivalent (0 dbm0) 0.7804 0.5024 0.5024 vrms -law digital mw or equivalent (0 dbm0) 0.7746 0.4987 0.4987 22,827 peak linear coded sine wave 0.7804 0.5024 0.5024 description test conditions min typ max unit note gain accuracy, d/a or a/d 0 dbm0, 1014 hz ax = ar = 0 db 0 to 85 c ?40 c ax = +6.02 db and/or ar = ?6.02 db 0 to 85 c ?40 c ?0.25 ?0.30 ?0.30 ?0.40 +0.25 +0.30 +0.30 +0.40 db gain accuracy digital-to-digital ?0.25 +0.25 gain accuracy analog-to-analog ?0.25 +0.25 attenuation distortion 300 hz to 3 khz ?0.125 +0.125 1 single frequency distortion ?46 2 second harmonic distortion, d-a gr = 0 db ?55 idle channel noise analog out digital out digital looped back weighted unweighted digital input = 0 a-law digital input = 0 -law analog v in = 0 vac a-law analog v in = 0 vac -law 0 0 ?68 ?55 ?78 12 ?68 16 dbm0p dbm0 dbm0p dbrnc0 dbm0p dbrnc0 3 3 3 3, 6 3 3, 6 crosstalk tx to rx same channel rx to tx 0 dbm0 300 to 3400 hz 0 dbm0 300 to 3400 hz ?75 ?75 dbm0 crosstalk between channels tx or rx to tx tx or rx to rx 0 dbm0 slic imped. < 300 ? 1014 hz, average 1014 hz, average ?76 ?78 dbm0 4 end-to-end group delay b = z = 0; x = r = 1 678 s 5
14 le58ql02/021/031 ve580 series data sheet 5. the end-to-end group delay is the sum of the transmit and rece ive group delays (both measured using the same time and clock s lot). 6. typical values not tested in production. attenuation distortion the signal attenuation in either path is nominally independent of the frequency. the deviations from nominal attenuation will s tay within the limits shown in figure 5 and figure 6 . the reference frequency is 1014 hz and the signal level is ? 10 dbm0. figure 5. transmit path attenuation vs. frequency figure 6. receive path attenuation vs. frequency average 20 10 1 20 ------ cf j () ? 10 1 20 ------ cf j1 ? () ? + 2 ---------------------------------------------------------------- f j f j1 ? --------- - ?? ?? ?? log ? j f n f 1 ---- - ?? ?? ?? log --------------------------------------------------------------------------------------------------------- log ? = 3 000 3 400 acceptable region 0.75 3 00 2 00 frequency (hz) 0 0 -0.125 0.125 attenuation (db) 0 1.8 3 000 3 400 2 0.6 acceptable region 0.65 6 00 3 00 2 00 0 3 200 0.80 0.2 attenuation (db) 1 frequency (hz) 0 -0.125 0.125
le58ql02/021/031 ve580 series data sheet 15 group delay distortion for either transmission path, the group delay distortion is within the limits shown in figure 7 . the minimum value of the group delay is taken as the reference. the signal level should be 0 dbm0. figure 7. group delay distortion 0 500 600 1 000 2 600 2 800 90 150 420 d elay (s) acceptable region frequency (hz)
16 le58ql02/021/031 ve580 series data sheet gain linearity the gain deviation relative to the gain at ?10 dbm0 is within the limits shown in figure 8 (a-law) and figure 9 ( -law) for either transmission path when the input is a sine wave signal of 1014 hz. figure 8. a-law gain linearity with tone input (both paths) figure 9. -law gain linearity with tone input (both paths) 0.55 0.25 0 -0.25 -0.55 -1.5 -55 -50 -40 -10 1.5 g ain (db) 0 acceptable region inpu t leve l (dbm0 ) +3 0.45 0.25 0 -0.25 -0.45 -1.4 -55 -50 -37 -10 1.4 g ain (db) 0 acceptable region +3 input leve l (dbm0 )
le58ql02/021/031 ve580 series data sheet 17 total distortion includin g quantizing distortion the signal to total distortion ratio will exceed the limits shown in figure 10 for either path when the input signal is a sine wave signal of frequency 1014 hz. figure 10. total distortion with tone input (both paths) input level (dbm0) signal-to-total distortion (db) acceptable region 0 -30 -40 -45 a a-law -law a 35.5db 35.5db b 35.5db 35.5db c 30db 31db d 25db 27db b c d
18 le58ql02/021/031 ve580 series data sheet discrimination against ou t-of-band input signals when an out-of-band sine wave signal of frequency f, and level a is applied to the analog input, there may be frequency components below 4 khz at the digital out put which are caused by t he out-of-band signal. these components are at least the specified db level below the level of a signal at the same outp ut originating from a 1014 hz sine wave signal with a level of a dbm0 also applied to the analog input. the minimu m specifications are shown in the following table. figure 11. discrimination against out-of-band signals note: the attenuation of the waveform below amplitude a, bet ween 3400 hz and 4600 hz, is given by the formula: discrimination against 12- and 16-khz metering signals if the qlslac device is used in a metering application where 12 khz or 16 khz tone bursts are injected onto the telephone line toward the subscriber, a portion of these tones also may a ppear at the vin terminal. these out-of-band signals may cause frequency components to appear below 4 khz at the digital output . for a 12 khz or 16 khz tone, the frequency components below 4 khz are reduced from the input by at least 70 db. the sum of the peak metering and signal voltages must be within the analog input voltage range. frequency of out-of-band signal amplitude of out-of-band signal level below a 16.6 hz < f < 45 hz ?25 dbm0 < a 0 dbm0 18 db 45 hz < f < 65 hz ?25 dbm0 < a 0 dbm0 25 db 65 hz < f < 100 hz ?25 dbm0 < a 0 dbm0 10 db 3400 hz < f < 4600 hz ?25 dbm0 < a 0 dbm0 see figure 11 4600 hz < f < 100 khz ?25 dbm0 < a 0 dbm0 32 db 0 -10 -20 -30 -40 level below a (db) -50 3.4 4.0 4.6 frequency (khz) -28 db -32 db attenuation (db) 14 14 4000 f ? () 1200 ----------------------------- ?? ?? sin ? =
le58ql02/021/031 ve580 series data sheet 19 spurious out-of-band signals at the analog output with pcm code words representing a sine wave signal in the range of 300 hz to 3400 hz at a level of 0 dbm0 applied to the digital input, the level of the spurious out-of-band signal s at the analog output is less than the limits shown below. with code words representing any sine wave signal in the range 3. 4 khz to 4.0 khz at a level of 0 dbm0 applied to the digital input, the level of the signals at the analog output are below the limits in figure 12 . the amplitude of the spurious out-of-band signals between 3400 hz and 4600 hz is given by the formula: figure 12. spurious out-of-band signals frequency level 4.6 khz to 40 khz ?32 dbm0 40 khz to 240 khz ?46 dbm0 240 khz to 1 mhz ?36 dbm0 level 14 ? 14 f 4000 ? () 1200 ----------------------------- ?? ?? sin ? dbm0 = 0 -10 -20 -30 -40 level (dbm0) -50 3.4 4.0 4.6 frequency (khz) -28 dbm0 -32 dbm0
20 le58ql02/021/031 ve580 series data sheet overload compression figure 13 shows the acceptable region of operation for input signal levels above the reference input power (0 dbm0). the conditions for this figure are: 1. 1.2 db < gx + 12 db 2. ?12 db gr < ?1.2 db 3. digital voice output connected to digital voice input. 4. measurement analog-to-analog. figure 13. analog-to-analog overload compression fundamental output power (dbm0) fundamental input power (dbm0) 1 2 3 4 5 6 7 8 9 123456 78 9 2.6 region acceptable
le58ql02/021/031 ve580 series data sheet 21 switching characteristics the following are the switching characteristics over operating r ange (unless otherwise noted). min and max values are valid for all digital outputs with a 115 pf load, except cd1?c5 with a 30 pf load. (see figure 15 and figure 16 for the microprocessor interface timing diagrams.) microprocessor interface pcm interface pclk not to exceed 8.192 mhz. pull-up resistors to v ccd of 240 ? are attached to tsca and tscb . (see figure 17 and figure 18 for the pcm interface timing diagrams.) no. symbol parameter min typ max unit note 1 t dcy data clock period 122 ns 2 t dch data clock high pulse width 48 3 t dcl data clock low pulse width 48 4 t dcr rise time of clock 25 5 t dcf fall time of clock 25 6 t icss chip select setup time, input mode 30 t dcy ?10 7 t icsh chip select hold time, input mode 0 t dch ?20 8 t icsl chip select pulse width, input mode 8t dcy 9 t icso chip select off time, input mode 2500 1 10 t ids input data setup time 25 11 t idh input data hold time 30 12 t olh slic device output latch valid 2500 13 t ocss chip select setup time, output mode 30 t dcy ?10 14 t ocsh chip select hold time, output mode 0 t dch ?20 15 t ocsl chip select pulse width, output mode 8t dcy 16 t ocso chip select off time, output mode 2500 1 17 t odd output data turn on delay 50 2 18 t odh output data hold time 3 19 t odof output data turn off delay 50 20 t odc output data valid 50 21 t rst reset pulse width 50 s no. symbol parameter min. typ max unit note 22 t pcy pcm clock period 122 ns 3 23 t pch pcm clock high pulse width 48 24 t pcl pcm clock low pulse width 48 25 t pcf fall time of clock 15 26 t pcr rise time of clock 15 27 t fss fs setup time 25 t pcy ?30 28 t fsh fs hold time 50 30 t tsd delay to tsc valid 5 80 4 31 t tso delay to tsc off 5 80 4, 5 32 t dxd pcm data output delay 5 70 33 t dxh pcm data output hold time 5 70 34 t dxz pcm data output delay to high-z 5 70 35 t drs pcm data input setup time 25 36 t drh pcm data input hold time 5
22 le58ql02/021/031 ve580 series data sheet master clock (see figure 19, master clock timing , on page 25 .) auxiliary output clocks notes: 1. if cfail = 1 (command 55h), gx, gr, z, b1, x, r, and b2 coe fficients must not be written or read without first deactivating a ll channels or switching them to default coefficients; otherwise, a chip select off time of 25 s is required. 2. the first data bit is enabled on the falling edge of cs or on the falling edge of dclk, whichever occurs last. 3. the pcm clock frequency must be an integer multiple of the frame sync frequency. the maximum allowable pcm clock frequency is 8.192 mhz. the actual pcm clock rate is dependent on the number of c hannels allocated within a frame. the minimum clock frequency is 128 khz in companded state and 256 khz in linear state, pcm signaling state, or double pclk state. the minimum pcm clock rates shou ld be doubled for parts with only one pcm highway in orde r to allow simultaneous acce ss to all four channels. 4. tsc is delayed from fs by a typical value of n ? t pcy , where n is the value stored in the time/clock-slot register. 5. t tso is defined as the time at which the output achieves t he open circuit state. 6. pclk and mclk are required to be integer multiples of the fram e sync (fs) frequency. frame sync is expected to be an accurate 8 khz pulse train. if pclk or mclk has jitter, care must be taken to ensure that all setup, hold, and pulse width requirements are me t. 7. phase jumps of 81 ns will be present when the master clock frequency is a multiple of 1.544 mhz. no. symbol parameter min typ max unit notes 37 j mcy master clock jitter 50 ns 6 38 t mcr rise time of clock 15 39 t mcf fall time of clock 15 40 t mch mclk high pulse width 48 41 t mcl mclk low pulse width 48 no. symbol parameter min typ max unit notes 42 f chp chopper clock frequency chp = 0 chp = 1 256 292.57 khz 7 42a dc chp chopper click duty cycle 50 % 7 43 f e1 e1 output frequency (cmode = ee1 = 1) 4.923 khz 7 44 t e1 e1 pulse width (cmode = ee1 = 1) 31.25 s 7
le58ql02/021/031 ve580 series data sheet 23 switching waveforms figure 14. input and output waveforms for ac tests figure 15. microprocessor interface (input mode) 2.0 v 0.8 v test points 2.4 v 0.45 v 2.0 v 0.8 v 1 5 v il dclk 4 cs data valid 11 d i/o 2 3 6 8 10 7 data valid v ih v il v ih 9 12 data valid data valid data valid outputs c5 - c1
24 le58ql02/021/031 ve580 series data sheet figure 16. microprocessor interface (output mode) figure 17. pcm highway timing for xe = 0 (transmit on negative pclk edge) dclk data valid data valid d i/o three-state v ol v oh data valid three-state v ih v il cs 13 17 20 18 15 14 16 19 first bit pclk fs dxa/dxb dra/drb first bit second bit v ol v oh v ih v il v ih v il tsca / tscb time slot zero clock slot zero 27 25 22 26 30 24 28 23 32 33 35 36 34 31
le58ql02/021/031 ve580 series data sheet 25 figure 18. pcm highway timing for xe = 1 (transmit on positive pclk edge) figure 19. master clock timing time slot zero clock slot zero first bit pclk fs dxa/dxb dra/drb first bit second bit v ol v oh tsca / tscb v ih v il v ih v il 22 25 31 34 33 35 36 27 30 32 28 23 24 26 v il v ih 40 37 41 39 38
26 le58ql02/021/031 ve580 series data sheet operating the qlslac device the following sections describe the operatio n of the four independent channels of the qlslac device. the description is valid for channel 1, 2, 3, or 4; consequently, the channel subscripts have been dropped. for example, vout refers to either vout1, vout2, vout3, or vout4. power-up sequence the recommended qlslac device power-up sequence is to apply: 1. analog and digital ground 2. vcc, signal connections, and low on rst 3. high on rst the software initialization should then include: 1. wait 1 ms. 2. select master clock frequency and source (command 46/47h). this should turn off the cfail bit (command 55h) within 400 s. 3. program filter coefficients and other parameters as required. 4. activate (command 0eh). if the power supply (vccd) falls below an internal threshold, t he device is reset and will require complete reprogramming with the above sequence. a reset may be initiated by connection of a logic low to the rst pin, or if chip select (cs ) is held low for 16 rising edges of dclk, a hardware reset is generated when cs returns high. the rst pin may be tied to vccd if it is not used in the system. channel enable (ec) register a channel enable register has been implemented in the qlslac device in order to reduce the effort required to address individual or multiple channels of the qlslac device. the regist er is written using mpi command 4a/4bh. each bit of the registe r is assigned to one unique channel, bit 0 for channel 1, bit 1 for channel 2, bit 2 for channel 3, and bit 3 for channel 4. the channel or channels are enabled when their corresponding enable bits ar e high. all enabled channels will receive the data written to th e qlslac device. this enables a broadcast mode (all channels enabled) to be implemented simply and efficiently, and multiple channel addressing is accomplished without incr easing the number of i/o pins on the dev ice. the broadcast mode can be further enhanced by providing the ability to select many chips at once; however, care must be taken not to enable more than one chip in the read state. this can lead to an internal bus contention, in which excess power is dissipated. (bus contention will not damage the device.) slic device control and data lines the qlslac device has up to five slic device programmable di gital input/output pins per chann el (cd1?c5). each of these pins can be programmed as either an input or an output using th e i/o direction register, command 54/55h (see figure 21). the output latches can be written with command 52h; however, only t hose bits programmed as outputs will actually drive the pins. the inputs can be read with command 53h. if a pin is programmed as an output, the data read from it will be the contents of the output latch. it is recommended that any of the slic device input/output control and data pins , which are to be programmed as outputs, be written to their desired state via command 52h before writing the data whic h configures them as outputs with the i/ o direction register command 54/55h. this ensures that when the ou tput is activated, it is alre ady in the correct state, and wi ll prevent unwanted data from being driv en from the slic device output pins. it is possible to make a slic device control output pull up to a non-standard voltage (v < 5.25 v) by connecting a resistor from the outp ut to the desired voltage, sending zero to the output, and using the dio bi t to tri-state the output. clock mode operation the qlslac device operates with multiple clock signals. the ma ster clock is used for internal timing including operation of the digital signal processing and may be derived from either the mclk or pclk source. when mclk is used as the master clock, it should be synchronous to fs. the allowed frequencies are listed under command 46/47h. the pcm clock (pclk) is used for pcm timing and is an integer mu ltiple of the frame sync frequency. the internal master clock can be optionally derived from the pclk sour ce by setting the cmode bit (bit 4, co mmand 46/47h) to one. in this mode, the mclk/e1 pin is free to be used as an e1 signal output. clo ck mode options and e1 output functions are shown in figure 20.
le58ql02/021/031 ve580 series data sheet 27 figure 20. clock mode options . e1 multiplex operation the qlslac device can multiplex input data from the cd1 slic device i/o pin into two separate status bits per channel (cd1 and cd1b bits in the slic input /output register, comm and 52/53h, and cda and cdb bits in the real time data register, command 4d/4fh) using the e1 multiplex mode. this multiplex mode provides the means to a ccommodate dual detect states when connected to an legerity slic device, which also supports ground-key detection in addition to loop detect. legerity slic devices that support ground-key detect use their e1 pin as an input to switch the slic device?s single detector (det) output between internal loop detect or ground-key det ect comparators. using the e1 multip lex mode, a single qlslac device can monitor both loop detect and ground-key detec t states of all four connected slic devi ces without additional hardware. although normally used for ground key detect, this multiplex function can also be used for monitoring other signal states. the e1 multiplex mode is selected by setting the ee1 bit (bit 7, command c8/c9h) and the cmode bit (bit 4, command 46/47h) in the qlslac device. the cmode bit must be selected (cmode=1) for the master clock to be derived from pclk so that the mclk/e1 pin can be used as an output for the e1 signal . the multiplex mode is then turned on by setting the ee1 bit. with the e1 multiplex mode enabled, the qlslac device generates the e1 output signal . this signal is a 31.25 s (1/32 khz) duration pulse occurring at a 4.923 khz (64 khz/13) rate. if ee1 is reset, mclk/e1 is programmed as an input and should be connected to ground if it is not connected to a clock source. the polarity of this e1 output is selected by the e1p bit (bit 6, command c8/c9h) allowing this multiplex mode to accommodate all slic devices regardless of their e1 high/low logic definition. figure 21 shows the slic device input/output register, i/o pins, e1 multiplex hardware operation for one qlslac device channel. it also shows the operation of the real time register. th e qlslac device e1 output signal connects directly to the e1 inputs of all four connected slic devices an d is used by those slic devices to select an internal comparator to route to the sl ic device det output. this e1 signal is also used internally by th e qlslac device for controlling the multiplex operation and timi ng. the cd1 and cd1b bits of the slic device input/output register are isolated from the cd1 pin by transparent latches. when the e1 pulse is off, the cd1 pin data is routed directly to the cd 1 bit of the slic device i/o register and changes to the cd1b bit of that register are disabled by its own latch. when e1 pulses on , the cd1 latch holds the last cd1 state in its register. at the same time, the cd1b latch is enabled, which allows cd1 pin data to be routed directly to the cd1b bit. therefore, during this multiplexing, the cd1 bit always has loop-detect status and the cd1b bit always has ground-key detect status. this multiplexing state changes almost instantaneously within the qlslac device but the slic device may require a slightly longer time period to respond to this detect state change befor e its det output settles and becomes valid. to accommodate this delay difference, the internal signals withi n the qlslac device are isolated by 15.625 s before allowing any change to the cd1 bit and cd1b bit latches. this operation is further described by the e1 multiplex timing diagram in figure 22. in this timing diagram, the e1 signal represents the act ual signal presented to the e1 output pin. the gk enable pulse allows cd1 pin data to time slot assigner dsp engine e1 pulses e1p pclk mclk/e1 n csel cmode (= 1) (= 0) e1 (= 1) (= 0) ee1 notes: 1. cmode = command 46/47h bit 4 2. csel = command 46/47h bits 0?3 3. ee1 = command c8/c9h bit 7 4. e1p = command c8/c9h bit 6 (= 0) (= 1)
28 le58ql02/021/031 ve580 series data sheet be routed through the cd1b latch. the ld enable pulse allows cd1 pin data to be routed through the cd1 latch. the uncertain states of the slic device?s det output, and the masked times wher e that det data is ignored are shown in this timing diagram. using this isolation of masked times, the cd1 and cd1b register s are guaranteed to contain accurate representations of the slic device detector output. figure 21. slic device i/o e1 multiplex and real-time data register operation note: * transparent latches: when enable input is high, q output follow s d input. when enable input goes low, q output is latched at last state. ?? cd1b c5 c4 c3 cd2 cd1 dq en/hold cd1 cd2 c3 c4 c5 dq en/hold 0 1 output latch i/o direction mpi command register ee1 bit slic output register mpi command 52h slic input register mpi command 53h ld enable * delay gk enable * e1 source e1p mclk/e1 mux cdb 1 cda 1 real time data register (command 4d/4fh) interrupt mask register (command 6c/6dh) (channel 1 shown) { same for channels 2, 3, 4 (command 70/71h) ati ground key filter (time set via command e8/e9h) mcdb 1 mcda 1 debounce (time set via command c8/c9h) int (internal) see figure 22 for details cda 4 cda 3 cda 2 cdb 4 cdb 3 cdb 2 mcdb 4 mcda 4 mcdb 3 mcda 3 mcdb 2 mcda 2 54/55h
le58ql02/021/031 ve580 series data sheet 29 figure 22. e1 multiplex internal timing debounce filters operation each channel is equipped with two debounce f ilter circuits to buffer the logic status of the cd1 and cd2/cd1b bits of the slic device input data register (command 53h) before providing filter ed bit?s outputs to the real-time data register (command 4d/ 4fh). one filter is used only for the cd1 bit. the other filter ac ts upon either the cd1b bit if e1 multiplexing is enabled, or on the cd2 bit if the multiplexing is not enabled. the cd1 bit normally contains slic device loop detect status . the cd1 debouncing time is programmable with the debounce time register (command c8/c9h), and even though each channel has its own filter, the programmed value is common to all four channels. this debounce filter is initia lly clocked at the frame sync rate of 125 s, and any occurrence of changing data at this sample rate resets a programmable counter. this progr ammable counter is clocked at a 1 ms rate, and the programmed count value of 0 to 15 ms, as defined by the debounce time regi ster, must be reached before updating the cda bit of the real time data register with the cd1 state. refer to figure 23 a for this filter?s operation. the ground-key filter (figure 23b) provides a buffering of the signal, normally ground key detect, which appears in the cd1b bi t of the real time data register. each channel has its own filter, and each filter?s time can be individually programmed. the inp ut to the filter comes from either the cd2 bi t of the slic device i/o data register (command 53h), when e1 multiplexing is not enabled, or from the cd1b bit of that r egister when e1 multiplexing is enabled. t he feature debounces ground-key signals before passing them to the real time data register, although signals other than ground-key status can be routed to the cd2 pin and then through the registers. the ground-key debounce filter oper ates as a duty-cycle detector and consists of an up/down counter which can range in value between 0 and 6. this six-state counter is clocked by the gk timer at the sampling period of 1?15 ms, as programmed by the value of the four gk bits (gk3, gk2, gk1, gk0) of the ground- key filter data register (command e8/e9h). this sampling period clocks the counter, which buffers the cd2/cd1b bit?s status before it is valid for presenting to the cdb bit of the real time d ata register. when the sampled value of the ground-key (or cd2) input is high, the counter is incremented by each clock pulse. when the sampled value is low, the counter is decremented. once the counter increments to its maximum value of 6, it sets a latch whose output is routed to the corresponding cdb bit. if the counter decrements to its minimum value of 0, this latch is cleared and the output bit is set to zero. all other times, the latch (and the cdb status) remains in its previous state without change . it therefore takes at least six consecutive gk clocks with the debounce in put remaining at th e same state to effect an output change. if the gk bit value is set to zero, the buffering is bypassed and the input status is passed directly to cdb. 31.25 s 4.923 khz (64 khz/13) pulse rate 15.625 s e1 gk enable ld enable 15.625 s 15.625 s pulse period 203.125 s det output from slic (cd1 pin input) contains valid gk status contains valid ld status contains valid ld status cd1 pin state ignored cd1 pin state ignored cd1 pin input data hold last state tracks det state cd1 register operation tracks det state cd1b register operation hold last state tracks det state hold last state
30 le58ql02/021/031 ve580 series data sheet figure 23. mpi real-time data register a. loop detect debounce filter notes: *transparent latch: output follows input when en is high; ouput holds last state when en is low. debounce counter: output is high after counting to programmed (dsh) number of 1 ms clocks; counter is reset for cd1 input chang es at 125 s sample period. dsh0 - dsh3 programmed value is common for all four channels, but debounce count er is separate per channel. b. ground-key filter notes: programmed value of gk0 - gk3 determines cl ock rate (1 - 15 ms) of six-state counter. if gk value = 0, the counter is bypassed and no buffering occurs. six-state up/down counter: counts up when input is high; counts down when input is low. output goes and stays high when maximum count is reached; output goes and stays low when count is down to zero. real-time data register operation to obtain time-critical data such as off/on-hook and ring trip information from the slic device with a minimum of processor tim e and effort, the qlslac device contains an 8-bit real time data register. this register contains cda and cdb bits from all four channels. the cda bit for each channel is a debounced version of the cd1 input. the cda bit is normally used for hook switch. the cdb bit for each channel normally contains the debounced value of the cd2 input bit; however, if the e1 multiplex operation is enabled, the cdb bit will contain the debounced value of the cd1b bit. cd1 and cd2 can be assigned to off-hook, ring trip, ground key signals, or other signals. frame sync is needed for th e debounce and the ground key signals. if frame sync is not provided, the real-time r egister will not work. the register is read using mpi command 4d/4fh, and may be read at any time regardless of the state of the channel enable register. this allo ws off/on-hook, ring trip, or ground key information for all f our channels to be obtained from the qlslac device with one read o peration versus one read per channel. if these data bits are not used for supervision information, they can be accessed on an individual channel basis in the same way as c3?c5; however, cd1 and cd1b will not be debounced. interrupt in addition to the real time data register, an interrupt signal has been implemented in the qlslac device. the interrupt signal is an active low output signal which pulls low whenever the unmasked cd bits change state (low to high or high to low); or whenever the transmit pcm data changes on a channel in which th e arm transmit interrupt (ati) bi t is on. the interrupt control is shown in figure 21 . the interrupt remains low until the appropriate regi ster is read. this output can be programmed as ttl or open drain. when an interrupt is generated, all of the unmasked bits in the real time data register latch and remain latched until the interrupt is cleared. the interrupt is cleared by read ing the register with command 4fh, by writing to the interrupt mask register (command 6ch), or by a reset. if any of the inputs to the unmasked bits in t he real time data register are different f rom 8 cd1 fs (8 khz) (0 ? 15 ms) dq q rst dsh0 ? dsh3 debounce period ck * dq dq dq debounce counter cda en/hold up/dn ground-key sampling interval gk0 ? gk3 1 ? 15 ms 1 khz clock divider (1 ? 15 ms clock output) gk = 0 gk = 0 mux gk cdb six-state up/down counter cd2 or cd1b rst q
le58ql02/021/031 ve580 series data sheet 31 the register bits when the interrupt is cleared by reading the register, a new interrupt is immediately generated with the new data latched into the real time data register. for this reason, th e interrupt logic in the controller should be level-sensitive rath er than edge-sensitive. interrupt mask register the real time data register data bits can be masked from causi ng an interrupt to the processor using the interrupt mask registe r. the mask register can be written or read via the mpi command 6c/6dh. active state each channel of the qlslac device can operate in either the active (operational) or inactive (standby) state. in the active sta te, individual channels of the qlslac device can transmit and receive pcm or linear data and analog information. the active state is required when a telephone call is in progress. the acti vate command (mpi command 0eh), puts the selected channel(s) into this state (see channel enable register). bringing a channel of t he qlslac device into the active state is only possible throug h the mpi. inactive state all channels of the qlslac device are forc ed into the inactive (standby) state by a power-up or hardware reset. individual channels can be programmed into this state by the deactivate command (command 00h) or by the software reset command (command 02h). power is disconnected from all nonessential circ uitry while the mpi remains active to receive commands. the analog output is tied to vref through a resistor whose value d epends on the vmode bit. all circuits that contain programmed information retain their data in the inactive state. chopper clock on the le58ql02jc there is a chopper clock output to drive th e switching regulator on some legerity slic devices. the clock frequency is selectable as 256 or 292.57 khz by the chp bit (command 46/47h). the duty cycle is given in the switching characteristics section. the chopp er output must be turned on wi th the ech bit (command c8/c9h). reset states the qlslac device can be reset by application of po wer, by an active low on the hardware reset pin (rst ), by a hardware reset command, or by cs low for 16 or more rising edges of dclk. this resets the qlslac device to the following state: 1. a-law companding is selected. 2. default b, x, r, and z filter values from rom are selected and the aisn is set to zero. 3. default digital gain blocks (gx, gr) from rom are selected. the analog gains, ax and ar, are set to 0 db and the input attenuator is turned on (dgin = 0). 4. the previously programmed b, z, x, r, gx, and gr filters in ram are unchanged. 5. slic device i/os (cd1?c5) are set to the input state. 6. all of the test states in the operati ng conditions register are turned off (0?s). 7. all four channels are in t he inactive (standby) state. 8. transmit time slots and receive time slots are set to 0, 1, 2, and 3 for channels 1, 2, 3, and 4, respectively. the clock slo ts are set to 0, with tran smit on the negative edge. 9. dxa port is selected for all channels. 10. dra port is selected for all channels. 11. the master clock frequency selected is 8.192 mhz and is programmed to come from pclk. 12. all four channels are selected in the channel enable register. 13. any pending interrupts are cleared, all interrupts are ma sked, and the interrupt output state is set to open drain. 14. the supervision debounce time is set to 8 ms. 15. the chopper clock frequency is set to 256 khz but the chopper clock is turned off. 16. the e1 multiplex state is turned off (e1 is hi-z) and the polarity is set for high going pulses. 17. no signalling on the pcm highway.
32 le58ql02/021/031 ve580 series data sheet signal processing overview of digital filters several of the blocks in the signal processing section are user programmable. these allow the user to optimize the performance of the qlslac device for the system. figur e 24 shows the qlslac device signal pr ocessing and indicate s the programmable blocks. the advantages of digital filters are: ? high reliability ? no drift with time or temperature ? unit-to-unit re peatability ? superior transmission performance ? flexibility ? maximum possible bandwidth for v.90 modems figure 24. qlslac device transmission block diagram two-wire impedance matching two feedback paths on the qlslac device synthesize the two- wire input impedance of the slic device by providing a programmable feedback path from vin to vout. the analog im pedance scaling network (aisn) is a programmable analog gain of ? 0.9375 ? gin to + 0.9375 ? gin from v in to v out . (see gin in electrical characteristics , on page 12 .) the z filter is a programmable digital filter providing an additional path and programming flexibility ov er the aisn in modifying the transfer function from vin to vout. together, the ai sn and the z-filter enable the user to syn thesize virtually all required slic device input impedances. frequency response corr ection and equalization the qlslac device contains programmable filters in the receiv e (r) and transmit (x) directi ons that may be programmed for line equalization and to correct any attenuat ion distortion caused by the z filter. transhybrid balancing the qlslac device?s programmable b filter is used to adjust tr anshybrid balance. the filter has a single pole iir section (biir ) and an eight-tap fir section (bfir), both operatin g at 16 khz. (see commands 86/87h and 96/97h.) gin v in ax aisn + ar adc dac inter- polator deci- mator + deci- mator inter- polator z b + gx x lpf & hpf gr r lpf ex- pander tsa tsa com- pressor high pass filter (hpf) full digital loopback (fdl) * * * * v out vref * ** ** lower receive gain (lrg) cutoff receive path (crp) tsa loopback (tlb) cutoff transmit path (ctp) digital tx digital rx 1 khz tone (ton) 0 * programmable blocks
le58ql02/021/031 ve580 series data sheet 33 gain adjustment the qlslac device?s transmit path has three programmable gai n blocks. gain block gin is an attenuator with a gain of gin (see electrical characteristics , on page 12 for the value). gain block ax is an analog gain of 0 db or 6.02 db (unity gain or gain of 2.0), located immediately befor e the a/d converter. gx is a digital gain block that is programmable from 0 db to +12 db, with a worst-case step size of 0.1 db for gain settings below +10 db, and a worst-case step size of 0.3 db for gain settings above + 10 db. the filters provide a net gain in the range of 0 db to 18 db. the qlslac device receive path has two pr ogrammable loss blocks. gr is a digital lo ss block that is programmable from 0 db to 12 db, with a worst-case step size of 0.1 db. loss block ar is an analog loss of 0 db or 6.02 db (unity gain or gain of 0.5) , located immediately after the d/a converter. this pr ovides a net loss in the range of 0 db to 18 db. an additional 6 db attenuation is provided as part of gr, which can be inserted by setting the lrg bit of command 70/71h. this allows writing of a single bit to introduce 6 db of att enuation into the receive path without having to reprogram gr. this 6 db loss is implemented as part of gr and the total re ceive path attenuation must remain in the specified 0 to ?12 db range. if the lrg bit is set, the programmed value of gr must not introdu ce more than an additional 6 db attenuation. transmit signal processing in the transmit path (a/d), the analog input signal (vin) is a/d converted, filtered, companded (for a-law or -law), and made available to the pcm highway in a-law, -law, or linear form . if linear form is selected, the 16-bit data will be transmitted i n two consecutive time slots starting at the progr ammed time slot. the signal processor contains an alu, ram, rom, and control logic to implement the filter sections. the b, x, and gx blocks are us er-programmable digital filter se ctions with coefficients store d in the coefficient ram, while ax is an analog amplifier that can be programmed for 0 db or 6.02 db gain. the b, x, and gx filters can also be operated from an alternate set of default coefficients stored in rom (command 60/61h). the decimator reduces the high input sampling rate to 16 khz for input to the b, gx, and x filters. the x filter is a six-tap f ir section which is part of the frequency resp onse correction network. the b filter operates on samples from the receive signal pa th in order to provide transhybrid balancing in the loop. the high-pa ss filter rejects low frequencies such as 50 hz or 60 hz, and may be disabled. transmit pcm interface the transmit pcm interface transmits a 16-bit linear code (when programmed) or an 8-bit compressed code from the digital a- law/-law compressor. transmit logic controls the transmission of data onto the pcm highway through output port selection and time/clock slot control circuitry. the linear data requires two cons ecutive time slots, while a single time slot is required fo r a-law/ -law data. in the pcm signaling state (smode = 1), the transmit time slot following the a-law or -law data is used for signaling information. the two time slots form a single 16-bit data block. the frame sync (fs) pulse identifies time sl ot 0 of the transmit frame and all channel s (time slots) are referenced to it. the logic contains user-programmable transmit time slot and transmit clock slot registers. the time slot register is 7 bits wide and allows up to 128 8-bi t channels (using a pclk of 8.192 mhz) in each frame. this featu re allows any clock frequency between 128 khz and 8.192 mhz (2 to 128 channels) in a system. the data is transmitted in bytes, with the most significant bit first. the clock slot register is 3 bits wide and may be programmed to offset the time slot assignment by 0 to 7 pclk periods to eliminate any clock skew in the system. an exception occurs when division of the pclk frequency by 64 khz produces a nonzero remainder, r, and when the transmit clock slot is greater than r. in that case, the r-bit fractional time slot after the last f ull time slot in the frame will contain random information and will have th e tsc output turned on. for exampl e, if the pclk frequency is 1.544 mhz (r = 1) and the transmit clock slot is greater than 1, th e 1-bit fractional time slot after the last full time slot in the frame will contain random information, and the tsc output will remain active during the fractional time slot. in such cases, problems can be avoided by not using the last time slot. the pcm data may be user programmed for output onto either the dxa or dxb port or both ports simultaneously. correspondingly, either tsca or tscb or both are low during transmission. the dxa/dxb and tsca /tscb outputs can be programmed to change either on the negative or positive edge of pclk. transmit data can also be read through the microprocessor interface using command cdh. receive signal processing in the receive path (d/a), the digital signal is expanded (for a-law or -law), filtered, converted to analog, and passed to th e vout pin. the signal processor contains an alu, ram, rom, and cont rol logic to implement the filter sections. the z, r, and gr blocks are user-programmable filter sections with their coefficients stor ed in the coefficient ram, wh ile ar is an analog ampli fier which can be programmed for a 0 db or 6.02 db loss. the z, r, and gr filters can also be operated from an alternate set of defau lt coefficients stored in rom (command 60/61h).
34 le58ql02/021/031 ve580 series data sheet the low-pass filter band limits the signal. t he r filter is composed of a six-tap fir section operating at a 16 khz sampling ra te and a one-tap iir section operating at 8 khz. it is part of the fre quency response correction network. the analog impedance scaling network (aisn) is a user-programmable gain block providing feedback from vin to vout to emulate different slic device input impedances from a single external slic device impedance. the z f ilter provides feedback from the transmit signal path to the receive path and is used to modify the effe ctive input impedance to the system. the in terpolator increases the sampling rate pr ior to d/a conversion. receive pcm interface the receive pcm interface logic controls the reception of data by tes from the pcm highway, transfers the data to the a-law/-la w expansion logic for compressed signals, and then passes the data to the receive path of the signal processor. if the data recei ved from the pcm highway is programmed for li near code, the a-law/-law expansion logic is bypassed and the data is presented to the receive path of the signal processor directly. the linear data requires two consecutive ti me slots, while the a-law or -law data requires a single time slot. the frame sync (fs) pulse identifies time slot 0 of the receive frame, and all channels (time slots) are referenced to it. the logic contains user-programmable receive time slot and receive clock slot registers. the time slot register is 7 bits wide and allows up to 128 8-bit c hannels (using a pclk of 8.192 mhz) in each frame. this feature allows any clock frequency between 128 khz and 8.192 mhz (2 to 128 ch annels) in a system. the clock slot register is 3 bits wide and can be programmed to offset the time sl ot assignment by 0 to 7 pclk periods to eliminate any clock skews in the system. an exception occurs when division of the pclk frequency by 64 khz produces a nonzero remainder (r), and when the receive clock slot is greater than r. in that case, the last full receive time slot in the frame is not usable. if the pclk frequency is 1.54 4 mhz (r=1), the receive clock slot can be only 0 or 1 if the last time slot is to be used. the pcm data can be programmed for input from the dra or drb port. analog impedance scaling network (aisn) the aisn is in the qlslac device to scale the value of the external slic device impedance. scaling this external impedance with the aisn (along with the z filter) allo ws matching of many different line cond itions using a single impedance value. line cards can meet many different specifications without any hardware changes. the aisn is a programmable transfer functi on connected from vin to vout of each ql slac device channel. the aisn transfer function can be used to alter the input impedance of the slic device to a new value (z in ) given by: where g 440 is the slic device echo gain into an open circuit, g 44 is the slic device echo gain into a short circuit, and z sl is the slic device input impedance without the qlslac device. the gain can be varied from ? 0.9375 ? gin to + 0.9375 ? gin in 31 steps of 0.0625 ? gin. the aisn gain is determined by the following equation: where each aisn i = 0 or 1 there are two special cases to the formula for h aisn : 1) a value of aisn = 00000 specifies a gain of 0 (or cutoff), and 2) a value of aisn = 10000 is a special case where the aisn circuitry is disabled and vout is connected internally to vin after the input attenuator with a gain of 0 db. this allows a full digital loopba ck state where an input digital pcm signal is completely proce ssed through the receive section, looped back, pr ocessed through the transmit section, and output as digital pcm data. during this test, the vin input is ignored and the vout output is connected to vref. speech coding the a/d and d/a conversion follows either the a-law or the -law standard as defi ned in itu-t recommendation g.711. a-law or -law operation is programmed using mp i command 60/61h. alternate bit inversion is performed as part of the a-law coding. the qlslac device provides linear code as an option on both t he transmit and receive sides of the device. linear code is selected using mpi command 60/61h. two successive time slots are required for linear code operation. the linear code is a 16- bit two?s-complement number which appears sign bit first on the pcm highway. linear code occupies two time slots. z in z sl 1g 44 h ? aisn ? ()? 1g 440 ? h aisn ? () ? = h aisn 0.0625 gin ? aisn i 2 i ? i0 = 4 ?? ?? ?? ?? 16 ? =
le58ql02/021/031 ve580 series data sheet 35 signaling on the pcm highway if the smode bit is set in the configurat ion register (command 46/47h), each data po int occupies two consecutive time slots. the first time slot contains a-law or -law data and the second time slot contains the following information: bit 7: debounced cd1 bit (usually hook switch) bit 6: cd2 bit or cd1b bit bits 5?3: reserved bit 2: cfail bits 1?0: reserved bit 7 of the signaling byte appears immediately after bit 0 of the data byte. a-law or -law companded state must be specified in order to put signaling information on the pcm highway. the signaling time slot remains active, even when the channel is inactiv e. robbed-bit signaling compatibility the qlslac device supports robbed bit signaling compatibility. robbed bit signaling allows periodic use of the least significan t bit (lsb) of the receive path pcm data to be used to carry sig naling information. in this scheme, separate circuitry within the line card or system intercepts this bit out of the pcm data stream and uses this bit to control signaling functions within the syste m. the qlslac device does not perform any processing of any of th e robbed bits during this operation; it simply allows for the robbed bit presence by performing the lsb substitution. if the rbe bit is set in the channel enable and operating m ode register (command 4a/4bh), then the robbed-bit signaling compatibility mode is enabled. robbed-bit signaling is only ava ilable in the -law companding mode of the device. also, only th e receive (digital-to-analog) path is involved. there is no cha nge of operation to the transmit path and pcm data coming out of t he qlslac device will always contain complete pcm byte data fo r each time slot, regardless of robbed-bit signaling selection. in the absence of actual pcm data for the af fected time slots, there is an uncertainty of the legitimate value of this bit to a ccurately reconstruct the analog signal. this bit can always be assumed to be a 1 or 0; hence, the reconstructed signal is correct half t he time. however, the other half of the time, there is an unacceptable reconstruction error of a significance equal to the value weighting of the lsb. to reduce this error and provide compatibility with the ro bbed bit signaling scheme, when in the robbed-b it signaling mode, the qlslac device ignores the lsb of each received pcm byte and replaces its value in the expander with a value of half the lsb?s weight. this then gua rantees the reconstruction is in error by only half this lsb weight. in the expand er, the eight bits of the companded pcm byte are expanded into linear pcm data of several more bits within the internal signal processing path of the device. therefore, ac curacy is not limited to the weight of the lsb, and a weight of half this value is realizable. when this robbed-bit mode is selected, not every frame contains bits for signaling, and therefore not every byte requires its l sb substituted with the half-lsb weight. this substitution only occurs for valid pcm time slots within frames for which this robbe d bit has been designated. to determine which time slots are affected, the device monitors the frame sync (fs) pulse. the current frame is a robbed-bit frame and this half-lsb va lue is used only when this criteria is met: ? the rbe bit is set, and ? the device is in the -law companding mode, and ? the current frame sync pulse (fs) is two pclk cycles long, and ? the previous frame sync pulse (fs) was not two pclk cycles long. the frame sync pulse is sampled on the falling edge of pclk. as shown in figure 25, if the above criteria is met, and if fs is high for two consecutive falling edges of pclk then low for th e third falling edge, it is cons idered a robbed-bit frame. otherw ise, it is a normal frame.
36 le58ql02/021/031 ve580 series data sheet figure 25. robbed-bit frame default filter coefficients the qlslac device contains an internal set of default coeffi cients for the programmable filters. the default filter gains are calculated based on the application circuit shown on page 60 . this slic device has a transmit gain of 0.5 (gtx) and a current gain of 500 (k1). the transmit relative level is set to +0.28 dbr, and the receive relative level is set to ?4.39 dbr. the equ alization filters (x and r) are not optimized and the z and b filters are set to zero. the nominal input impedance was set to 812 ? . if the slic device circuit differs significantly from this design, the default gains cannot be used and must be replaced by programmed coefficients. the balance filter (b) must always be programmed to an appropriate value. to obtain this above-system response, the default filter coefficients are set to produce these values: gx gain = +6 db, gr gain = ?8.984 db ax gain = 0 db, ar gain = 0 db, input attenuator on (dgin = 0) r filter: h(z) = 1, x filter: h(z) = 1 z filter: h(z) = 0 b filter: h(z) = 0 aisn = cutoff notice that these default coefficient values are retained in a read-only memory area within the qlslac device, and those values cannot be read back using any data commands. when the device is selected to use default coefficients, it obtains those values directly from the read-only memory area, where the coefficient read operations access the programmable random access data memory only. if an attempt is made to read back any filter valu es without those values first being written with known programme d data, the values read back are totally random and do not represent the default or any other values. pclk fs normal frame (not robbed-bit) robbed-bit frame pclk fs
le58ql02/021/031 ve580 series data sheet 37 command descript ion and formats command field summary a microprocessor can program and control the qlslac device us ing the mpi. data programmed previously can be read out for verification. see the tables below for the channel and global chip parameters assigned. commands are provided to assign values to the following channel parameters: commands are provided to read values from the following channel monitors: table 3. channel parameters parameter description mpi tts transmit time slot 40/41h rts receive time slot 42/43h gx transmit gain 80/81h gr receive loss 82/83h b 1 b 1 filter coefficients 86/87h b 2 b 2 filter coefficients 96/97h x x filter coefficients 88/89h r r filter coefficients 8a/8bh zfir z-fir filter coefficients 98/99h ziir z-iir filter coefficients 9a/9bh z z filter coefficients (both fir and iir) 84/85h aisn aisn coefficient 50/51h cd1?c5 write slic device outputs 52h iod1?5 slic device input/output direction 54/55h a/ select a-law or -law 60/61h c/l compressed/linear 60/61h tpcm select transmit pcm highway a or b 40/41h tab select transmit pcm on highway selected by tpcm, or on both ports a and b 44/45h rpcm select receive pcm port a or b 42/43h eb programmed/default b filter 60/61h ez programmed/default z filter 60/61h ex programmed/default x filter 60/61h er programmed/default r filter 60/61h egx programmed/default gx filter 60/61h egr programmed/default gr filter 60/61h dgin disable input attenuator 50/51h ax enable/disable ax amplifier 50/51h ar enable/disable ar amplifier 50/51h ctp cutoff transmit path 70/71h crp cutoff receive path 70/71h hpf disable high pass filter 70/71h lrg lower receive gain 70/71h ati arm transmit interrupt 70/71h ilb interface loopback 70/71h fdl full digital loopback 70/71h ton 1 khz tone on 70/71h gk ground-key filter e8/e9h cstat select active or inactive (standby) state 55h, 00h, 0eh
38 le58ql02/021/031 ve580 series data sheet commands are provided to assign values to the following global chip parameters: commands are provided to read values from the following global chip status monitors: microprocessor interface description the following description of the mpi (microprocessor interface) is valid for channels 1 ? 4. if desired, multiple channels can be programmed simultaneously with identical information by settin g multiple channel enable bits. channel enables are contained in the channel enable register and written or read using mpi comma nd 4a/4bh. if multiple channel enable bits are set for a read operation, only data from the first enabled channel will be read. the mpi physically consists of a serial data input/out put (dio), a data clock (dclk), and a chip select (cs ). individual channel enable bits ec1, ec2, ec3, and ec4 are stored internally in the channel enable register of the qlslac device. the serial input consists of 8-bit commands that can be followed wi th additional byte s of input data, or can be followed by the qlslac device sending out bytes of data. all data input and output is m sb (d7) first and lsb (d0) last. all data bytes are read or wri tten one at a time, with cs going high for at least a minimum off period before the next byte is read or written. only a single channel should be enabled during read commands. all commands that require additional input da ta to the device must have the input data as the next n words written into the dev ice (for example, framed by t he next n transitions of cs ). all unused bits must be programmed as 0 to ensure compatibility with future parts. all commands that are followed by output data will caus e the device to output data for the next n transitions of cs going low. the qlslac device will not accept any commands until all t he data has been shifted out. the output values of unused bits are not specified. an mpi cycle is defined by transitions of cs and dclk. if the cs lines are held in the high state between accesses, the dclk may run continuously with no change to the internal control data. using this method, the same dc lk can be run to a number of table 4. channel monitors monitor description mpi cd1?c5 read slic device inputs 53h cd1b multiplexed slic device input 53h xdat transmit pcm data cdh table 5. global chip parameters parameter description mpi xe transmit pcm clock edge 44/45h rcs receive clock slot 44/45h tcs transmit clock slot 44/45h intm interrupt output drive mode 46/47h chp chopper clock frequency 46/47h ech enable chopper clock output c8/c9h smode select signaling on the pcm highway 46/47h cmode select master clock mode 46/47h csel select master clock frequency 46/47h rbe robbed bit enable 4a/4bh vmode vout mode 4a/4bh ec channel enable register 4a/4bh dsh debounce time for cd1 c8/c9h ee1 enable e1 output c8/c9h e1p e1 polarity c8/c9h mcdx c interrupt mask register 6c/6dh table 6. global chip status monitors monitor description mpi cd x c real time data register 4d/4fh cfail clock failure bit 54/55h rcn revision code number 73h
le58ql02/021/031 ve580 series data sheet 39 qlslac devices and the individual cs lines will select the appropriate device to access. between command sequences, dclk can stay in the high state indefinitely with no loss of in ternal control information regardless of any transitions on the cs lines. between bytes of a multibyte read or write command sequence, dc lk can also stay in the high state indefinitely. dclk can stay in the low state indefinitely with no loss of internal control information, provided the cs lines remain at a high level. if a low period of cs contains less than 8 positive dclk transitions, it is i gnored. if it contains 8 to 15 positive transitions, only the last 8 transitions matter. if it contains 16 or more posit ive transitions, a hardware reset in the part occurs. if the chip is in the middle of a read sequence when cs goes low, data will be present at the dio pin even if dclk has no activity. summary of mpi commands note: *all codes not listed are rese rved by legerity and should not be used. mpi command structure this section details each mpi command. each command is shown along with the format of any additional data bytes that follow. for details of the filter coefficients of the form c xy m xy , refer to the general description of csd coefficients section page 55 . unused bits are indicated by ?rsvd?; 0?s should be writt en to them, but 0?s are not gua ranteed when they are read. *default field values are marked by an asterisk. a hardware reset forces the default values. hex* description 00h deactivate (standby state) 02h software reset 04h hardware reset 06h no operation 0eh activate (operational state) 40/41h write/read transmit time slot and pcm highway selection 42/43h write/read receive time slot and pcm highway selection 44/45h write/read rec & tx clock slot and tx edge 46/47h write/read configuration register 4a/4bh write/read channel enable & operating mode register 4dh read real time data register 4fh read real time data register and clear interrupt 50/51h write/read aisn and analog gains 52/53h write/read slic device input/output register 54/55h write/read slic device input/output direction and status bits 60/61h write/read operating functions 6c/6dh write/read interrupt mask register 70/71h write/read operating conditions 73h read revision code number (rcn) 80/81h write/read gx filter coefficients 82/83h write/read gr filter coefficients 84/85h write/read z filter coefficients (fir and iir) 86/87h write/read b1 filter coefficients (fir) 88/89h write/read x filter coefficients 8a/8bh write/read r filter coefficients 96/97h write/read b2 filter coefficients (iir) 98/99h write/read z filter coefficients (fir only) 9a/9bh write/read z filter coefficients (iir only) c8/c9h write/read debounce time register cdh read transmit pcm data e8/e9h write/read ground key filter sampling interval
40 le58ql02/021/031 ve580 series data sheet 00h deactivate (standby state) in the deactivate (standby) state: all programmed information is retained. the microprocessor interfac e (mpi) remains active. the pcm inputs are disabled and the pcm outputs are high impedance unless signaling on the pcm high way is programmed (smode = 1). the analog output (vout) is disabled and biased at vref. the channel status (cstat) bit in the slic device i/o direction and channel status register is set to 0. 02h software reset the action of this command is identical to that of the rst pin except that it only operates on the channels selected by the channel enable register and it does not change clock slots, ti me slots, pcm highways ground key sampling interval, or global chip parameters. see the note under the hardware reset command that follows. 04h hardware reset hardware reset is equivalent to pulling the rst on the device low. this command does not depend on the state of the channel enable register. note: the action of a hardware reset is described in reset states on page 31 of the section operating the qlslac device . 06h no operation 0eh activate channel (operational state) this command places the device in the active state and sets cstat = 1. no valid pcm data is transmitted until after the third fs pulse is received following the execution of the activate command. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 00000000 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 00000010 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 00000100 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 00000110 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 00001110
le58ql02/021/031 ve580 series data sheet 41 40/41h write/read transmit time slot and pcm highway selection r/w = 0: write r/w = 1: read transmit pcm highway tpcm = 0* transmit on highway a (see tab in command 44/45h) tpcm = 1 transmit on highway b (see tab in command 44/45h) transmit time slot tts = 0?127 time slot number (tts0 is lsb, tts6 is msb) pcm highway b is not available on the le58ql021/031 qlslac devices. * power up and hardware reset (rst ) value = 00h, 01h, 02h, 03h for chann els 1, 2, 3, and 4, respectively. 42/43h write/read receive time slot and pcm highway selection r/w = 0: write r/w = 1: read receive pcm highway rpcm = 0* receive on highway a rpcm = 1 receive on highway b receive time slot rts = 0?127 time slot number (rts0 is lsb, rts6 is msb) pcm highway b is not available on the le58ql021 and the le58ql031 qlslac devices. * power up and hardware reset (rst ) value = 00h, 01h, 02h, 03h for channe ls 1, 2, 3, and 4, respectively. 44/45h write/read transmit clock slot, receive clock sl ot, and transmit clock edge r/w = 0: write r/w = 1: read transmit on a and b tab = 0* transmit data on highway selected by tpcm (see command 40/41h on page 41 ). tab = 1 transmit data on both highways a and b transmit edge xe = 0* transmit changes on negative edge of pclk xe = 1 transmit changes on positive edge of pclk receive clock slot rcs = 0*?7 receive clock slot number transmit clock slot tcs = 0*?7 transmit clock slot number the xe bit and the clock slots apply to all four channels; however , they cannot be written or r ead unless at least one channel is selected in the channel enable register. * power up and hardware reset (rst ) value = 00h. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 0 100000r/w i/o data tpcm tts6 tts5 tts4 tts3 tts2 tts1 tts0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 0 100001r/w i/o data rpcm rts6 rts5 rts4 rts3 rts2 rts1 rts0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 0 100010r/w i/o data tab xe rcs2 rcs1 rcs0 tcs2 tcs1 tcs0
42 le58ql02/021/031 ve580 series data sheet 46/47h write/read chip configuration register r/w = 0: write r/w = 1: read interrupt mode intm = 0 ttl-compatible output intm = 1* open drain output chopper clock control chp = 0* chopper clock is 256 khz (2048/8 khz) chp = 1 chopper clock is 292.57 khz (2048/7 khz) pcm signaling mode smode = 0* no signaling on pcm highway smode = 1 signaling on pcm highway clock source mode cmode = 0 mclk used as master clock; no e1 multiplexing allowed cmode = 1* pclk used as master clock; e1 mult iplexing allowed if enabled in commands c8/c9h. the master clock frequency can be selected by csel. th e master clock frequency sele ction affects all channels. master clock frequency csel = 0000 1.536 mhz csel = 0001 1.544 mhz csel = 0010 2.048 mhz csel = 0011 reserved csel = 01xx two times frequency specified above (2 x 1.536 mhz, 2 x 1.544 mhz, or 2 x 2.048 mhz) csel = 10xx four times frequency specified above (4 x 1.536 mhz, 4 x 1.544 mhz, or 4 x 2.048 mhz) csel = 11xx reserved csel = 1010* 8.192 mhz is the default these commands do not depend on the state of the channel enable register. * power up and hardware reset (rst ) value = 9ah. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 0 1 0 0 0 1 1 r/w i/o data intm chp smode cmode csel3 csel2 csel1 csel0
le58ql02/021/031 ve580 series data sheet 43 4a/4bh write/read channel enab le and operating mode register r/w = 0: write r/w = 1: read rsvd reserved for future use. always write as 0, but 0 is not guaranteed when read. robbed-bit mode rbe = 0* robbed-bit signaling mode is disabled. rbe = 1 robbed-bit signaling mode is enabled on pcm receiver if -law is selected. vout mode vmode = 0* vout = vref through a resistor when channel is deactivated vmode = 1 vout high impedance when channel is deactivated. low power mode lpm lpm reduced the power in the qslac device, but it is not needed and not used in the qlslac device channel enable 4 ec4 = 0 disabled, channel 4 cannot receive commands ec4 = 1* enabled, channel 4 can receive commands channel enable 3 ec3 = 0 disabled, channel 3 cannot receive commands ec3 = 1* enabled, channel 3 can receive commands channel enable 2 ec2 = 0 disabled, channel 2 cannot receive commands ec2 = 1* enabled, channel 2 can receive commands channel enable 1 ec1 = 0 disabled, channel 1 cannot receive commands ec1 = 1* enabled, channel 1 can receive commands * power up and hardware reset (rst ) value = 0fh. 4d/4fh read real-time data register c = 0: do not clear interrupt c = 1: clear interrupt this register reads real-time data with or without clearing the interrupt. real time data cda1 debounced data bit 1 on channel 1 cdb1 data bit 2 or multiplexed data bit 1 on channel 1 cda2 debounced data bit 1 on channel 2 cdb2 data bit 2 or multiplexed data bit 1 on channel 2 cda3 debounced data bit 1 on channel 3 cdb3 data bit 2 or multiplexed data bit 1 on channel 3 cda4 debounced data bit 1 on channel 4 cdb4 data bit 2 or multiplexed data bit 1 on channel 4 this command does not depend on the state of the channel enable register. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 01 0 0101r/w i/o data rsvd rbe vmode lpm ec4 ec3 ec2 ec1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 0 10011c1 output data cdb4 cda4 cdb3 cda3 cdb2 cda2 cdb1 cda1
44 le58ql02/021/031 ve580 series data sheet 50/51h write/read aisn and analog gains r/w = 0: write r/w = 1: read disable input attenuator (gin) dgin = 0* input attenuator on dgin = 1 input attenuator off transmit analog gain ax = 0* 0 db gain ax = 1 6.02 db gain receive analog loss ar = 0* 0 db loss ar = 1 6.02 db loss aisn coefficient aisn = 0* ? 31 see below (default value = 0) the impedance scaling network (aisn) gain can be varied from ? 0.9375 ? gin to + 0.9375 ? gin in multiples of 0.0625 ? gin. the gain coefficient is decoded using the following equation: where h aisn is the gain of the aisn. a value of aisn = 10000 turns on the full digital loopback mode and a value of aisn = 0000* indicates a gain of 0 (cutoff). * power up and hardware reset (rst ) value = 00h. 52/53h write/read slic d evice input/output register r/w = 0: write r/w = 1: read rsvd reserved for future use. always write as 0, but 0 is not guaranteed when read. pins cd1, cd2, and c3 through c5 are set to 1 or 0. the data appears latched on the cd1, cd2, and c3 through c5 slic device i/o pins, provided they were set in th e output mode (see command 54/55h on page page 44 ). the data sent to any of the pins set to the input mode is latched, but does not appear at the pins. the cd1b bit is only valid if the e1 multiplex mode is enabled (ee1 = 1). * power up and hardware reset (rst ) value = 00h 54/55h write/read slic input/out put direction, read status bits r/w = 0: write r/w = 1: read rsvd reserved for future use. always write as 0, but 0 is not guaranteed when read. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 0 101000r/w i/o data dgin ax ar aisn4 aisn3 aisn2 aisn1 aisn0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 0 101001r/w i/o data rsvd rsvd cd1b c5 c4 c3 cd2 cd1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 0 1 01010r/w input data rsvd cstat cfail iod5 iod4 iod3 iod2 iod1 h aisn 0.0625 gin ? = 16 aisn4 8 aisn3 4 aisn2 2 aisn1 aisn0 + ? + ? + ? + ? () 16 ? []
le58ql02/021/031 ve580 series data sheet 45 channel status (read status only, write as 0) cstat = 0 channel is inactive (standby state). cstat = 1 channel is active. clock fail (read status only, write as 0) cfail* = 0 the internal clock is synchronized to frame synch. cfail = 1 the internal clock is not synchronized to frame synch. * the cfail bit is independent of the channel enable register. i/o direction (read/write) iod5 = 0* c5 is an input iod5 = 1 c5 is an output iod4 = 0* c4 is an input iod4 = 1 c4 is an output iod3 = 0* c3 is an input iod3 = 1 c3 is an output iod2 = 0* cd2 is an input iod2 = 1 cd2 is an output iod1 = 0* cd1 is an input iod1 = 1 cd1 is an output pins cd1, cd2, and c3 through c5 are set to input or output modes individually . pins c3?c5 are not available on the le58ql031 qlslac device, and c5 is available only on the le58ql021 qlslac device. * power up and hardware reset (rst ) value = 00h 60/61h write/read operating functions r/w = 0: write r/w = 1: read linear code c/l = 0* compressed coding c/l = 1 linear coding a-law or -law a/ = 0* a-law coding a/ = 1 -law coding gr filter egr = 0* default gr filter enabled egr = 1 programmed gr filter enabled gx filter egx = 0* default gx filter enabled egx = 1 programmed gx filter enabled x filter ex = 0* default x filter enabled ex = 1 programmed x filter enabled r filter er = 0* default r filter enabled er = 1 programmed r filter enabled z filter ez = 0* default z filter enabled ez = 1 programmed z filter enabled b filter eb = 0* default b filter enabled eb = 1 programmed b filter enabled * power up and hardware reset (rst ) value = 00h. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 0 110000r/w i/o data c/l a/ egr egx ex er ez eb
46 le58ql02/021/031 ve580 series data sheet 6c/6dh write/read interrupt mask register r/w = 0: write r/w = 1: read mask cd interrupt mcdx c = 0 cdx c bit is not masked mcdx c = 1* cdx c bit is masked x bit number (a or b) c channel number (1 through 4) masked: a change does not cause the interrupt pin to go low. this command does not depend on the state of the channel enable register. * power up and hardware reset (rst ) value = ffh. 70/71h write/read operating conditions r/w = 0: write r/w = 1: read cutoff transmit path ctp = 0* transmit path connected ctp = 1 transmit path cut off cutoff receive path crp = 0* receive path connected crp = 1 receive path cutoff (see note) high pass filter hpf = 0* transmit highpass filter enabled hpf = 1 transmit highpass filter disabled lower receive gain lrg = 0* 6 db loss not inserted lrg = 1 6 db loss inserted arm transmit interrupt ati = 0* transmit interrupt not armed ati = 1 transmit interrupt armed interface loopback ilb = 0* tsa loopback disabled ilb = 1 tsa loopback enabled full digital loopback fdl = 0* full digital loopback disabled fdl = 1 full digital loopback enabled 1 khz receive tone ton = 0* 1 khz receive tone off ton = 1 1 khz receive tone on * power up and hardware reset (rst ) value = 00h. the b filter is disabled during receive cutoff. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 0110110r/w i/o data mcdb4 mcda4 mcdb3 mcda3 mcdb2 mcda2 mcdb1 mcda1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 0 1 1 1 0 0 0 r/w i/o data ctp crp hpf lrg ati ilb fdl ton
le58ql02/021/031 ve580 series data sheet 47 73h read revision c ode number (rcn) this command returns an 8-bit number (rcn) describing the revision number of the qlslac device. the revision code of the qlslac device will be 14h or higher. this command does not depend on the state of the channel enable register. 80/81h write/read gx filter coefficients r/w = 0: write r/w = 1: read cxy = 0 or 1 in the command above corresponds to cxy = + 1 or ? 1, respectively, in the equation below. the coefficient for the gx filter is defined as: power up and hardware reset (rst ) values = a9f0 (hex) (h gx = 1.995 (6 db)). note: the default value is contained in a rom register separate from t he programmable coefficient ram. there is a filter enable bit i n operating func- tions register to switch between the default and programmed values. 82/83h write/read gr filter coefficients r/w = 0: write r/w = 1: read cxy = 0 or 1 in the command above corresponds to cxy = + 1 or ? 1, respectively, in the equation below. the coefficient for the gr filter is defined as: power up and hardware reset (rst ) values = 23a1 (hex) (h gr = 0.35547 (?8.984 db)). see note under command 80/81h, above. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 0 1 1 1 0 0 1 1 i/o data rcn7 rcn6 rcn5 rcn4 rcn3 rcn2 rcn1 rcn0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 1 0 0 0 0 0 0 r/w i/o data byte 1 c40 m40 c30 m30 i/o data byte 2 c20 m20 c10 m10 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command: 1 0 0 0 0 0 1 r/w i/o data byte 1 c40 m40 c30 m30 i/o data byte 2 c20 m20 c10 m10 h gx 1c10 ( 2 m10 ? 1c202 m20 ? 1c302 m30 ? ? 1c402 m40 ? ? + () + [] ? + {} ? + = h gr c10 2 m10 ? 1c202 m20 ? 1c302 m30 ? ? 1c402 m40 ? ? + () + [] ? + {} ? =
48 le58ql02/021/031 ve580 series data sheet 84/85h write/read z filter coefficients (fir and iir) r/w = 0: write r/w = 1: read this command writes and reads both the fi r and iir filter sect ions simultaneously. cxy = 0 or 1 in the command above corresponds to cxy = + 1 or ? 1, respectively, in the equation below. the z-transform equation for t he z filter is defined as: sample rate = 32 khz for i = 0 to 5 and 7 power up and hardware reset (rst ) values = 0190 0190 0190 0190 0190 0190 01 0190 (hex) (h z (z) = 0) see note under command 80/81h on page 47 . note: z 6 is used for iir filter scaling only. its value is typically greater than zero but less than or equal to one. the input to the iir filter section is first increased by a gain of 1/z 6 , improving dynamic range and avoiding truncat ion limitations through processing with in this filter. the iir filter output is then multiplied by z 6 to normalize the overall gain. z 5 is the actual iir filter gain value defined by the programmed coefficients, but it also in- cludes the initial 1/z 6 gain. the theoretical effective iir gain, without the z 6 gain and normalizati on, is actually z 5 /z 6 . d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 1000010r/w i/o data byte 1 c40 m40 c30 m30 i/o data byte 2 c20 m20 c10 m10 i/o data byte 3 c41 m41 c31 m31 i/o data byte 4 c21 m21 c11 m11 i/o data byte 5 c42 m42 c32 m32 i/o data byte 6 c22 m22 c12 m12 i/o data byte 7 c43 m43 c33 m33 i/o data byte 8 c23 m23 c13 m13 i/o data byte 9 c44 m44 c34 m34 i/o data byte 10 c24 m24 c14 m14 i/o data byte 11 c45 m45 c35 m35 i/o data byte 12 c25 m25 c15 m15 i/o data byte 13 c26 m26 c16 m16 i/o data byte 14 c47 m47 c37 m37 i/o data byte 15 c27 m27 c17 m17 h z z () z 0 z 1 z 1 ? ? z 2 z 2 ? ? z 3 z 3 ? ? z 4 z 4 ? z 5 z 6 ? z 7 z 1 ? ? ? 1z 7 z ? 1 ? ? ------------------------------------------ - + ? ++++ = z i c1i 2 m1i ? ? 1c2i2 m2i ? 1c3i2 m3i ? ? 1c4i2 m4i ? ? + () + [] ? + {} = z 6 c16 2 m16 ? ? 1c262 m26 ? ? + {} =
le58ql02/021/031 ve580 series data sheet 49 86/87h write/read b1 filter coefficients r/w = 0: write r/w = 1: read cxy = 0 or 1 in the command above corresponds to cxy = + 1 or ? 1, respectively, in the equation below. the z-transform equation for t he b filter is defined as: sample rate = 16 khz the coefficients for the fir b section and t he gain of the iir b section are defined as: for i = 2 to 10, the feedback coefficient of the iir b section is defined as : refer to command 96/97h for programming of the b 11 coefficients. power up and hardware reset (rst ) values = 09 00 90 09 00 90 09 00 90 09 00 90 09 00 (hex) see note under command 80/81h on page 47 . rsvd reserved for future use. always write as 0, but 0 is not guaranteed when read. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 1000011r/w i/o input data byte 1 c32 m32 c22 m22 i/o input data byte 2 c12 m12 c33 m33 i/o input data byte 3 c23 m23 c13 m13 i/o input data byte 4 c34 m34 c24 m24 i/o input data byte 5 c14 m14 c35 m35 i/o input data byte 6 c25 m25 c15 m15 i/o input data byte 7 c36 m36 c26 m26 i/o input data byte 8 c16 m16 c37 m37 i/o input data byte 9 c27 m27 c17 m17 i/o input data byte 10 c38 m38 c28 m28 i/o input data byte 11 c18 m18 c39 m39 i/o input data byte 12 c29 m29 c19 m19 i/o input data byte 13 c310 m310 c210 m210 i/o input data byte 14 c110 m110 rsvd rsvd h b z () b 2 z 2 ? b 9 ++ ? z 9 ? ? b 10 z 10 ? ? 1b 11 z 1 ? ? ? -------------------------------- + = b i c1i 2 mli ? ? 1 c2i 2 m2i ? ? 1c3i2 m3i ? ? + () + [] = b 11 c111 2 m111 ? ? 1 c211 2 m211 ? ? 1c3112 m311 ? 1 c411 2 m411 ? ? + () ? + [] + {} = h b z ) 0 = (
50 le58ql02/021/031 ve580 series data sheet 88/89h write/read x filter coefficients r/w = 0: write r/w = 1: read cxy = 0 or 1 in the command above corresponds to cxy = + 1 or ? 1, respectively, in the equation below. the z-transform equation for t he x filter is defined as: sample rate = 16 khz for i = 0 to 5, the coefficients for the x filter are defined as: power up and hardware reset (rst ) values = 0111 0190 0190 0190 0190 0190 (hex) (h x (z) = 1) see note under command 80/81h on page 47 . d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 1000100r/w i/o input data byte 1 c40 m40 c30 m30 i/o input data byte 2 c20 m20 c10 m10 i/o input data byte 3 c41 m41 c31 m31 i/o input data byte 4 c21 m21 c11 m11 i/o input data byte 5 c42 m42 c32 m32 i/o input data byte 6 c22 m22 c12 m12 i/o input data byte 7 c43 m43 c33 m33 i/o input data byte 8 c23 m23 c13 m13 i/o input data byte 9 c44 m44 c34 m34 i/o input data byte 10 c24 m24 c14 m14 i/o input data byte 11 c45 m45 c35 m35 i/o input data byte 12 c25 m25 c15 m15 h x z () x 0 x 1 z 1 ? x 2 z 2 ? x 3 z 3 ? x 4 z 4 ? x 5 z 5 ? +++++ = xi c1i 2 m1i ? ? 1c2i2 m2i ? 1 c3i 2 m3i ? ? 1c4i2 m4i ? ? + () + [] ? + {} =
le58ql02/021/031 ve580 series data sheet 51 8a/8bh write/read r filter coefficients r/w = 0: write r/w = 1: read cxy = 0 or 1 in the command above corresponds to cxy = + 1 or ? 1, respectively, in the equation below. the z-transform equation for t he iir filter is defined as: sample rate = 8 khz the coefficient for the iir filter is defined as: the z-transform equation for t he fir filter is defined as: sample rate = 16 khz for i = 0 to 5, the coefficients for the r2 filter are defined as: power up and hardware reset (rst ) values = 2e01 0111 0190 0190 0190 0190 0190 (hex) (h fir (z) = 1, r 6 = 0.9902) see note under command 80/81h on page 47 . d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 1000101r/w i/o input data byte 1 c46 m46 c36 m36 i/o input data byte 2 c26 m26 c16 m16 i/o input data byte 3 c40 m40 c30 m30 i/o input data byte 4 c20 m20 c10 m10 i/o input data byte 5 c41 m41 c31 m31 i/o input data byte 6 c21 m21 c11 m11 i/o input data byte 7 c42 m42 c32 m32 i/o input data byte 8 c22 m22 c12 m12 i/o input data byte 9 c43 m43 c33 m33 i/o input data byte 10 c23 m23 c13 m13 i/o input data byte 11 c44 m44 c34 m34 i/o input data byte 12 c24 m24 c14 m14 i/o input data byte 13 c45 m45 c35 m35 i/o input data byte 14 c25 m25 c15 m15 hr h = iir h fir ? h iir 1z 1 ? ? 1r 6 z 1 ? ? ?? ?? ? ----------------------------------- - = r 6 c16 2 ml6 ? ? 1 c26 2 m26 ? 1c362 m36 ? ? 1c462 m46 ? ? + () + [] ? + {} = h fir z () r 0 r 1 z 1 ? r 2 z 2 ? r 3 z 3 ? r 4 z 4 ? r 5 z 5 ? +++++ = r i c1i 2 m1i ? ? 1c2i2 m2i ? 1c3i2 m3i ? ? 1c4i2 m4i ? ? + () + [] ? + {} =
52 le58ql02/021/031 ve580 series data sheet 96/97h write/read b2 filt er coefficients (iir) r/w = 0: write r/w = 1: read this function is described in write/read b1 filter coefficients (fir) on page 49 . power up and hardware reset (rst ) values = 0190 (hex) (b 11 = 0) see note under command 80/81h on page 47 . 98/99h write/read fir z filter coefficients (fir only) r/w = 0: write r/w = 1: read this command writes and reads only the fi r filter section without affecting the iir. cxy = 0 or 1 in the command above corresponds to cxy = + 1 or ? 1, respectively, in the equation below. the z-transform equation for t he z filter is defined as: sample rate = 32 khz for i = 0 to 5 and 7 power up and hardware reset (rst ) values = 0190 0190 0190 0190 0190 0190 01 0190 (hex) (h z (z) = 0) see note under command 80/81h on page 47 . note: z 6 is used for iir filter scaling only. its value is typically greater than zero but less than or equal to one. the input to the iir filter section is first increased by a gain of 1/z 6 , improving dynamic range and avoiding truncat ion limitations through processing with in this filter. the iir filter output d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 1001011r/w i/o data byte 1 c411 m411 c311 m311 i/o data byte 2 c211 m211 c111 m111 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 1001100r/w i/o data byte 1 c40 m40 c30 m30 i/o data byte 2 c20 m20 c10 m10 i/o data byte 3 c41 m41 c31 m31 i/o data byte 4 c21 m21 c11 m11 i/o data byte 5 c42 m42 c32 m32 i/o data byte 6 c22 m22 c12 m12 i/o data byte 7 c43 m43 c33 m33 i/o data byte 8 c23 m23 c13 m13 i/o data byte 9 c44 m44 c34 m34 i/o data byte 10 c24 m24 c14 m14 h z z () z 0 z 1 z 1 ? ? z 2 z 2 ? ? z 3 z 3 ? ? z 4 z 4 ? z 5 z 6 z 7 z 1 ? ? ? ? 1z 7 z ? 1 ? ? ------------------------------------------ - + ? ++++ = z i c1i 2 m1i ? ? 1c2i2 m2i ? 1c3i2 m3i ? ? 1c4i2 m4i ? ? + () + [] ? + {} = z 6 c16 2 m16 ? ? 1c262 m26 ? ? + {} =
le58ql02/021/031 ve580 series data sheet 53 is then multiplied by z 6 to normalize the overall gain. z 5 is the actual iir filter gain value defined by the programmed coefficients, but it also in- cludes the initial 1/z 6 gain. the theoretical effective iir gain, without the z 6 gain and normalizati on, is actually z 5 /z 6 . 9a/9bh write/read iir z filt er coefficients (iir only) r/w = 0: write r/w = 1: read this command writes/reads the iir filter section only, without affecting the fir. cxy = 0 or 1 in the command above corresponds to cxy = + 1 or ? 1, respectively, in the equation below. the z-transform equation for t he z filter is defined as: sample rate = 32 khz for i = 0 to 5 and 7 power up and hardware reset (rst ) values = 0190 0190 0190 0190 0190 0190 01 0190 (hex) (h z (z) = 0) see note under command 80/81h on page 47 . note: z 6 is used for iir filter scaling only. its value is typically great er than zero but less than or equal to one. the input to the iir filter section is first increased by a gain of 1/z 6 , improving dynamic range and avoiding truncation limitations through processing within this filter. the iir filter out put is then multiplied by z 6 to normalize the overall gain. z 5 is the actual iir filter gain value defined by the programmed coefficients, but it also includes the initial 1/z 6 gain. the theoretical effective iir gain, without the z 6 gain and normalization, is actually z 5 /z 6 . c8/c9h write/read debounce time register this command applies to all channels and does not depend on the state of the channel enable register. r/w = 0: write r/w = 1: read enable e1 ee1 = 0* e1 multiplexing turned off ee1 = 1 e1 multiplexing turned on e1 polarity e1p = 0* e1 is a high-going pulse e1p = 1 e1 is a low-going pulse d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 1001101r/w i/o data byte 1 c45 m45 c35 m35 i/o data byte 2 c25 m25 c15 m15 i/o data byte 3 c26 m26 c16 m16 i/o data byte 4 c47 m47 c37 m37 i/o data byte 5 c27 m27 c17 m17 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 1100100r/w i/o data ee1 e1p dsh3 dsh2 dsh1 dsh0 rsvd ech h z z () z 0 z 1 z 1 ? ? z 2 z 2 ? ? z 3 z 3 ? ? z 4 z 4 ? z 5 z 6 z 7 z 1 ? ? ? ? 1z 7 z ? 1 ? ? ------------------------------------------ - + ? ++++ = z i c1i 2 m1i ? ? 1c2i2 m2i ? 1c3i2 m3i ? ? 1c4i2 m4i ? ? + () + [] ? + {} = z 6 c16 2 m16 ? ? 1c262 m26 ? ? + {} =
54 le58ql02/021/031 ve580 series data sheet there is no e1 output unless cmode = 1. debounce for hook switch dsh = 0?15 debounce period in ms dsh contains the debouncing time (in ms) of the cd1 data (usually hook switch) entering the real time data register described earlier. the input data must remain stable for the debouncing time in order to change the appropriate real time bit. default = 8 ms rsvd reserved for future use. always write as 0, but 0 is not guaranteed when read. enable chopper ech = 0* chopper output (chclk) turned off ech = 1 chopper output (chclk) turned on * power up and hardware reset (rst ) value = 20h. cdh read transmit pcm data rsvd reserved for future use. always write as 0, but 0 is not guaranteed when read. upper transmit data xdat contains a-law or -law transmit data in companded mode. xdat contains upper data byte in linear mode with sign in xdat7. e8/e9h write/read ground key filter r/w = 0: write r/w = 1: read filter ground key gk = 0?15 filter sampling period in 1 ms gk contains the filter sampling time (in ms) of the cd1b data (usually ground key) or cd2 enter ing the real time data register described earlier. a value of 0 disables the gr ound key filter for that particular channel. power up and hardware reset (rst ) value = x0h. rsvd reserved for future use. always write as 0, but 0 is not guaranteed when read. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 11001101 output data byte 1 xdat7 xdat6 xdat5 xdat4 xdat3 xdat2 xdat1 xdat0 output data byte 2 rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 command 1110100r/w i/o data rsvd rsvd rsvd rsvd gk3 gk2 gk1 gk0
le58ql02/021/031 ve580 series data sheet 55 programmable filters general description of csd coefficients the filter functions are performed by a seri es of multiplications and accumulations. a multiplication occurs by repeatedly shif ting the multiplicand and summing the result with the previous value at that summation no de. the method used in the qlslac device is known as canonic signed digit (csd) multiplication and splits each coefficient into a series of csd coefficients. each programmable fir filter section has the following general transfer function: equation 1 where the number of taps in the filter = n + 1. the transfer function for the iir part of z and b filters: equation 2 the transfer function of the iir part of the r filter is: equation 3 the values of the user-defined coefficients (h i ) are assigned via the mpi. each of the coefficients (h i ) is defined in the following general equation: equation 4 where: mi = the number of shifts = mi mi + 1 b i = sign = 1 n = number of csd coefficients. h i in equation 4 represents a decimal number, broken down into a sum of successive values of: 1) 1.0 multiplied by 2 ?0 , or 2 ?1 , or 2 ?2 ? 2 ?7 ? 2) 1.0 multiplied by 1, or 1/2, or 1/4 ? 1/128 ? the limit on the negative powers of 2 is determ ined by the length of the registers in the alu. the coefficient h i in equation 4 is a value made up of n binary 1s in a bi nary register where the left part represents whole numbers, the right part decimal fractions, and a decimal point separates them. the first binary 1 is shifted m 1 bits to the right of the decimal point; the second binary 1 is shifted m 2 bits to the right of the decimal point; the third binary 1 is shifted m 3 bits to the right of the decimal point, and so on. when m 1 is 0, the value is a binary 1 in front of the decimal point, that is, no shift. if m 2 is also 0, the result is another binary 1 in front of the decimal point, giving a total value of binary 10 in front of the decimal point (i.e ., a decimal value of 2.0). the value of n, therefore, determines the ra nge of values the coefficient h i can take (e.g., if n = 3 the maximum and minimum values are 3, and if n = 4 the values are between 4). detailed description of ql slac device coefficients the csd coding scheme in the qlslac device uses a value call ed mi, where m1 represents the distance shifted right of the decimal point for the first binary 1. m2 represents the distance shifted to the right of the previous binary 1, and m3 represen ts the number of shifts to the right of the second binary 1. note that the range of values determined by n is unchanged. equation 4 is now modified (in the case of n = 4) to: equation 5 equation 6 equation 7 where: m 1 = m1 b 1 = c1 m 2 = m1 + m2 b 2 = c1 ? c2 hf z () h 0 h 1 z 1 ? h 2 z 2 ? h n z n ? ++++ = hi z () 1 1h n1 + () z 1 ? ? ----------------------------------- = hi z () 1z 1 ? ? 1h n1 + () z 1 ? ? ----------------------------------- = h i b 1 2 m1 ? b 2 2 m2 ? b n 2 mn ? +++ = h i b 1 2 m1 ? b 2 2 m2 ? b 3 2 m3 ? b 4 2 m4 ? +++ = h i c1 2 ? m1 ? c1 c ? 22 ? m1 m2 + () ? c1 c ? 2c ? 32 ? m1 m2 m3 ++ () ? c1 c2 ? c3 c4 2 ? ? ? m1 m2 m3 m 4 +++ ( ? ++ + = h i c1 2 ? m1 ? 1c22 ? m2 ? 1c32 ? m3 ? 1c42 ? m4 ? + () + [] + {} =
56 le58ql02/021/031 ve580 series data sheet m 3 = m1 + m2 + m3 b 3 = c1 ? c2 ? c3 m 4 = m1 + m2 + m3 + m4 b 4 = c1 ? c2 ? c3 ? c4 in the qlslac device, a coefficient, h i , consists of n csd coefficients, each being made up of 4 bits and formatted as c xy m xy , where c xy is 1 bit (msb) and m xy is 3 bits. each csd coefficient is broken down as follows: c xy is the sign bit (0 = positive, 1 = negative). m xy is the 3-bit shift code. it is encoded as a binary number as follows: 000: 0 shifts 001: 1 shifts 010: 2 shifts 011: 3 shifts 100: 4 shifts 101: 5 shifts 110: 6 shifts 111: 7 shifts y is the coefficient number (the i in h i ). x is the position of this cs d coefficient within the h i coefficient. the most significant binary 1 is represented by x = 1. the next most significant binary 1 is represented by x = 2, and so on. thus, c13 m13 represents the sign and the relative shift po sition for the first (most sign ificant) binary 1 in the 4th (h 3 ) coefficient. the number of csd coefficients, n, is limited to 4 in the gr, gx , r, x, and z filters; 4 in the iir part of the b filter; 3 in the fir part of the b filter; and 2 in the post-gain factor of the z-iir filter. the gx filter coefficient equ ation is slightly differe nt from the other filters. equation 8 please refer to the summary of mpi commands on page 39 for complete details on programming the coefficients. user test states and operating conditions the qlslac device supports testing by providing test states and special operating conditions as shown in figure 21 (see operating conditions register). cutoff transmit path (ctp): when ctp = 1, dx and tsc are high impedance and the transmit time slot does not exist. this state takes precedence over the tsa loopback (tlb) and full digital loopback (fdl) states. cutoff receive path (crp): when crp = 1, the receive signal is forced to 0 just ahead of the low pass filter (lpf) block. this state also blocks full digital loopback (fdl), the 1 khz receive tone, and the b-filter path. high pass filter disable (hpf): when hpf = 1, all of the high pass and notch filters in the transmit path are disabled. lower receive gain (lrg): when lrg = 1, an extra 6.02 db of loss is inserted into the receive path. arm transmit interrupt (ati) and read transmit pcm data: the read transmit pcm data command, command cdh, can be used to read transmit pcm data through the microprocessor interf ace. if the ati bit is set, an interrupt will be generated when ever new transmit data appears in the channel and will be cleared when the data is read. when combined with tone generation and loopback states, this allows the micr oprocessor to test channel integrity. tsa loopback (tlb): when tlb = 1, data from the tsa receive path is looped back to the tsa transmit path. any other data in the transmit path is overwritten. full digital loopback (fdl): when fdl = 1, the vout output is turned off and the analog output voltage is routed to the input of the transmit path, replacing the voltage from vin. the aisn path is temporarily turned off. this test mode can also be enter ed by writing the code 10000 into the aisn register. 1 khz receive tone (ton): when ton = 1, a 1 khz digital mw is injected into the receive path, replacing any receive signal from the tsa. a-law and -law companding table table 7 and table ta b l e 8 show the companding definitions used for a-law and -law pcm encoding. h igx 1h i + =
le58ql02/021/031 ve580 series data sheet 57 table 7. a-law: positive input values notes: 1. 4096 normalized value units correspond to tmax = 3.14 dbm0. 2. the character signals are obtained by inverting the even bits of the signals of column 6. before this inversion, the characte r signal corresponding to positive input values betw een two successive decision values numbered n and n+1 (see column 4) is 128+n, expre ssed as a binary number. 3. the value at the decoder output is , for n = 1,...127, 128. 4. x 128 is a virtual decision value. 5. bit 1 is a 0 for negative input values. 12345 678 segment # intervals x interval size value at segment end points decision value number n decision value x n ( see note 1 ) character signal pre inversion of even bits quantized value (at decoder output) y n decoder output value no. bit no. number 1 2 3 4 5 6 7 8 4096 (128) (4096) 7 6 5 4 1 1 1 1 1 1 1 1 4032 128 3968 127 2048 1024 113 112 97 96 see note 2 1 1 1 1 0 0 0 0 2176 2048 2112 113 see note 2 1 1 1 0 0 0 0 0 1088 1024 1056 97 512 81 80 see note 2 1 1 0 1 0 0 0 0 544 512 528 81 256 65 64 see note 2 1 1 0 0 0 0 0 0 272 256 264 65 3 128 49 48 see note 2 1 0 1 1 0 0 0 0 136 128 132 49 2 64 33 32 see note 2 1 0 1 0 0 0 0 0 68 64 66 33 1 1 0 see note 2 1 0 0 0 0 0 0 0 2 0 11 16 x 128 16 x 64 16 x 32 16 x 16 16 x 8 16 x 4 32 x 2 y n x n 1 ? x n + 2 ------------------------ - =
58 le58ql02/021/031 ve580 series data sheet table 8. -law: positive input values notes: 1. 8159 normalized value units correspond to tmax = 3.17 dbm0. 2. the character signal corresponding to posi tive input values between two successive decision values numbered n and n+1 (see co lumn 4) is 255-n, expressed as a binary number. 3. the value at the decoder is y 0 = x 0 = 0 for n = 0, and , for n = 1, 2,...127. 4. x 128 is a virtual decision value. 5. bit 1 is a 0 for negative input values. 12345 678 segment # intervals x interval size value at segment end points decision value number n decision value x n ( see note 1 ) character signal pre inversion of even bits quantized value (at decoder output) y n decoder output value no. bit no. number 1 2 3 4 5 6 7 8 8159 (128) (8159) 8 7 6 5 1 0 0 0 0 0 0 0 8031 127 7903 127 4063 2015 113 112 97 96 see note 2 1 0 0 0 1 1 1 1 4319 4063 4191 112 see note 2 1 0 0 1 1 1 1 1 2143 2015 2079 96 991 81 80 see note 2 1 0 1 0 1 1 1 1 1055 991 1023 80 479 65 64 see note 2 1 0 1 1 1 1 1 1 511 479 495 64 4 223 49 48 see note 2 1 1 0 0 1 1 1 1 239 223 231 48 3 95 33 32 see note 2 1 1 0 1 1 1 1 1 103 95 99 32 2 17 16 see note 2 1 1 1 0 1 1 1 1 35 31 00 16 x 256 16 x 128 16 x 64 16 x 32 16 x 16 16 x 8 16 x 4 33 16 31 1 x 1 1 2 1 see note 2 1 1 1 1 1 1 1 0 3 1 15 x 2 21 1 1 1 1 1 1 1 1 00 y n x n1 + x n + 2 ------------------------- =
le58ql02/021/031 ve580 series data sheet 59 applications the qlslac device performs a programmable codec/filter function for four telephone lines. it interfaces to the telephone lines through a legerity slic device or a transfor mer with external buffering. the qlslac device provides latched digital i/o to cont rol and monitor four slic devices and provides access to time-criti cal information, such as off/on-hook and ring trip, for all four channels via a single read operation. when various country or transmission requirements must be met, the qlslac device enables a single slic device design for multiple applications. th e line characteristics (such as apparent impedanc e, attenuatio n, and hybrid balance) can be modified by programming each ql slac device channel?s coefficients to meet desired performance. the qlslac device may require an external buffer to drive transformer slic devices. connection to a pcm back plane is implemented by means of a simple buffer chip. several qlslac devices can be tied together in one bus interfacing the back plane through a single buffer. an intelligent bus interface chip is not required because each qlslac device provides its own buffer control (tsxa/b). th e qlslac device is controlled through the microprocessor interface, either by a microprocessor on the line card or by a central processor. controlling the slic device the le58ql021 qlslac device has five ttl-compatible i/o pins (cd1, cd2, c3 to c5) for each channel. the le58ql031 qlslac device has only cd1 and cd2 available. the output s are programmed using command 52h, and the status is read back using command 53h. cd1 and cd2 for all four channels c an be read back using command 4d/4fh. the direction of the i/o pins (input or output) is specified by programming t he slic device i/o direction register (command 54/55h). calculating coefficients with winslac software the winslac software is a program that models the qlslac device, the line conditions, the slic device, and the line card components to obtain the coefficients of the programmable f ilters of the qlslac device and some of the transmission performance plots. the following parameters relating to the desired line conditions and the components/circuits used in the line card are to be provided as input to the program: 1. line impedance or the balance impedance of the li ne is specified by the local telephone system. 2. desired two-wire impedance that is to appear at the line card terminals of the exchange. 3. tabular data for templates describing the frequency response and attenuation distortion of the design. 4. relative analog signal levels for both the transmit and receive two-wire signals. 5. component values and slic device selection for the analog portion of the line circuits. 6. two-wire return loss template is usual ly specified by the local telephone system. 7. four-wire return loss template is usually specified by the local telephone system. the output from the winslac program includes the coefficients of the gr, gx, z, r, x, and b filters as well as transmission performance plots of two-wire return loss, receive and trans mit path frequency responses, and four-wire return loss. the software supports the use of the leger ity slic devices or allows entry of a spi ce netlist describing the behavior of any ty pe of slic device circuit.
60 le58ql02/021/031 ve580 series data sheet application circuit figure 26. le7920 slic/qlslac device application circuit line card parts list the following list defines the parts and part values requir ed to meet target specification limits for one channel. note: for all other components, please refer to the le7920 data sheet, document id #080146. item quantity type value tol. rating comments c bpa 1 capacitor 0.1 f 20% 10 v bypass capacitor c bpd 1 capacitor 0.1 f 20% 10 v bypass capacitor c fil 1 capacitor 0.1 f 20% 10 v bypass capacitor c vtx 1 capacitor 0.1 f 20% 10 v coupling capacitor r rx 1 resistor 57.6 k ? 1% 0.01 w c vrx 1 capacitor 0.15 f 20% 10 v r t 1 resistor 178 k ? 1% 0.01 w r fa 1 fuse resistor 50 ? see note r fb 1 fuse resistor 50 ? test out rr tip tip ring slic 2 3 da db ax hpa hpb bx ryout1, ryout2 ryout3 bgnd vbat tmg vcc rd agnd u1 le7920 slic vtx rsn rdc c1, c2 d0 d1 det cas ring bus r sr4 c rt c th r rth2 r r1 tip r sr1 r fa c ad u3 rr c hp c bd shared ring threshold ring to ti test in k rr k ti k to + 5v slic 3 ring slic 4 tip ring r fb vbat bgnd vbat c bat d1 r tmg c dc r t r d c as vcca vin1 agnd cd21, c31 vout1 cd11 5 5 5 c d c41 c51 c bpa c vrx vref mlck/e1 pclk fs dxa dio dra dclk mclk/e1 pclk fs dxa dio dra pcm/mpi c vtx r rx r dc1 r dc2 2 vccd c fil tsca tsca dclk cs cs rst rst int int dgnd c bpd + 3.3 v + 5.0 v analog ground digital ground u2 le58ql021 qlslac
le58ql02/021/031 ve580 series data sheet 61 physical dimensions 32-pin plcc
62 le58ql02/021/031 ve580 series data sheet 44-pin plcc dwg rev. an; 8/00 plcc 044 plcc 044
le58ql02/021/031 ve580 series data sheet 63 44-pin tqfp dwg rev. as; 08/00 tqfp 044 tqfp 044
revision history revision a1 to a2 ? changed titles for physical dimensions graphics to more industry-standard names revision a2 to b1 ? added information regarding the input at tenuator gain (gin) throughout document ? made minor edits to the "product description" section ? removed references to resistors r out1 and r out2 from "application circuit" and "line card parts list" revision b1 to c1 ? added a maximum vcc current limit of 0.5 a to the absolute maximum ratings if the rise ra te of vcc is greater than 0.4 v/s ? decreased the digital leakage allowed from 15 to 7 a ? increased the standby power to 13 mw typical and 18 mw maximum ? in transmission characteristics, sec ond harmonic distortion, added gr=0 db; added d-a in description field ? added a nominal spec on the chopper clock duty cycle ? added a note warning the user of 81 ns phase jumps on chclk and e1 when the master clock is a multiple of 1.544 mhz ? modified the power-up sequence ? at e1 multiplex operation, added "if ee1 is reset, mclk/e 1 is programmed as an input and should be connected to ground if it is not connected to a clock source" ? clarified interrupt section wording by adding a phrase ? at reset states, when e1 multiplex state is turned off, added "(e1 is hi-z)" revision c1 to d1 ? added green package opns to description , on page 1 ? added package assembly , on page 11 revision d1 to e1 ? added "packing" column and note 2 to ordering information , on page 1 revision e1 to f1 ? modified gaisn specification in electrical characteristics , on page 12 .
the contents of this document are provided in connection with legerity, inc. products. legerity makes no representations or war ranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time with out notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in legerity's standard te rms and conditions of sale, legerity assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. legerity's products are not designed, intend ed, authorized or warranted for use as co mponents in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur. legerity reserves the right to discontinue or make changes to its products at any time without notice. ? 2006 legerity, inc. all rights reserved. trademarks legerity, the legerity logo and combinations thereof are regist ered trademarks, and batterydirect, islic, islac, phoneport, qsl ac, qlslac, voiceedge, voicepath, voiceport, the "v" in vo ip and winslac are trademarks of legerity, inc. other product names and marks used within this document are fo r identification purposes only and may be registered trademarks o r trademarks of their respective companies.
4509 freidrich lane austin, texas 78744-1812 telephone: (512) 228-5400 fax: (512) 228-5508 north america toll free: (800) 432-4009 to find the legerity sales office nearest you, visit our website at: http://www.legerity.com/sales or email: sales@legerity.com to download or order data sheets, application notes, or evaluation tools, go to: www.legerity.com/support for all other technical inquiries, please contact legerity tech support at: techsupport@legerity.com or call +1 512.228.5400. ?

▲Up To Search▲

Price & Availability of LE58QL021FJC

	To Download LE58QL021FJC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .